x86/registers/
task.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2025.
4
5// This is inspired and adapted for Tock from the [x86](https://github.com/gz/rust-x86) crate.
6
7//! Helpers to program the task state segment.
8//! See Intel 3a, Chapter 7
9
10pub use super::segmentation;
11
12#[cfg(target_arch = "x86")]
13use core::arch::asm;
14
15/// Returns the current value of the task register.
16///
17/// # Safety
18/// Needs CPL 0.
19#[cfg(target_arch = "x86")]
20pub unsafe fn tr() -> segmentation::SegmentSelector {
21    let segment: u16;
22    unsafe {
23        asm!("str {0:x}",
24            out(reg) segment,
25            options(att_syntax, nostack, nomem, preserves_flags));
26    }
27    segmentation::SegmentSelector::from_raw(segment)
28}
29
30/// Loads the task register.
31/// # Safety
32/// Needs CPL 0.
33#[cfg(target_arch = "x86")]
34pub unsafe fn load_tr(sel: segmentation::SegmentSelector) {
35    unsafe {
36        asm!("ltr {0:x}",
37            in(reg) sel.bits(),
38            options(att_syntax, nostack, nomem, preserves_flags));
39    }
40}
41
42//For CI only
43
44#[cfg(not(any(doc, target_arch = "x86")))]
45pub unsafe fn tr() -> segmentation::SegmentSelector {
46    unimplemented!()
47}
48
49#[cfg(not(any(doc, target_arch = "x86")))]
50pub unsafe fn load_tr(_sel: segmentation::SegmentSelector) {
51    unimplemented!()
52}
x86/registers/task.rs

x86/registers/
task.rs
