litex_sim/
litex_generated_constants.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5#![allow(unused)]
6
7// LiteX SoC Wishbone Register format
8pub type SoCRegisterFmt = litex_vexriscv::litex_registers::LiteXSoCRegistersC32B32;
9
10// constants defined in `generated/soc.h`
11
12pub type ClockFrequency = kernel::hil::time::Freq1MHz;
13
14pub const CONFIG_CPU_HAS_INTERRUPT: bool = true;
15pub const CONFIG_CPU_RESET_ADDR: usize = 0;
16
17pub const CONFIG_CPU_TYPE: &str = "vexriscv";
18pub const CONFIG_CPU_VARIANT: &str = "secure";
19pub const CONFIG_CPU_HUMAN_NAME: &str = "VexRiscv_Secure";
20pub const CONFIG_CPU_NOP: &str = "nop";
21
22pub const CONFIG_CSR_DATA_WIDTH: usize = 32;
23pub const CONFIG_CSR_ALIGNMENT: usize = 32;
24pub const CONFIG_BUS_STANDARD: &str = "WISHBONE";
25pub const CONFIG_BUS_DATA_WIDTH: usize = 32;
26pub const CONFIG_BUS_ADDRESS_WIDTH: usize = 32;
27
28pub const ETHMAC_RX_SLOTS: usize = 2;
29pub const ETHMAC_TX_SLOTS: usize = 2;
30pub const ETHMAC_SLOT_SIZE: usize = 2048;
31
32pub const GPIO_INTERRUPT: usize = 3;
33pub const ETHMAC_INTERRUPT: usize = 2;
34pub const TIMER0_INTERRUPT: usize = 1;
35pub const UART_INTERRUPT: usize = 0;
36
37// constants defined in `generated/csr.h`
38pub const CSR_BASE: usize = 0xf0000000;
39pub const CSR_CTRL_BASE: usize = CSR_BASE + 0x0000;
40pub const CSR_ETHMAC_BASE: usize = CSR_BASE + 0x0800;
41pub const CSR_ETHPHY_BASE: usize = CSR_BASE + 0x1000;
42pub const CSR_GPIO_BASE: usize = CSR_BASE + 0x1800;
43pub const CSR_IDENTIFIER_MEM_BASE: usize = CSR_BASE + 0x2000;
44pub const CSR_TIMER0_BASE: usize = CSR_BASE + 0x2800;
45pub const CSR_UART_BASE: usize = CSR_BASE + 0x3000;
46
47// constants defined in `generated/mem.h`
48pub const MEM_ETHMAC_BASE: usize = 0x80000000;
49pub const MEM_ETHMAC_SIZE: usize = 0x00002000;