cortexm7/
lib.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Shared implementations for ARM Cortex-M7 MCUs.
6
7#![crate_name = "cortexm7"]
8#![crate_type = "rlib"]
9#![no_std]
10
11use core::fmt::Write;
12
13pub mod mpu {
14    pub type MPU = cortexm::mpu::MPU<16, 32>; // Cortex-M7 MPU has 16 regions
15}
16
17pub use cortexm::initialize_ram_jump_to_main;
18pub use cortexm::nvic;
19pub use cortexm::scb;
20pub use cortexm::support;
21pub use cortexm::systick;
22pub use cortexm::unhandled_interrupt;
23pub use cortexm::CortexMVariant;
24
25// Enum with no variants to ensure that this type is not instantiable. It is
26// only used to pass architecture-specific constants and functions via the
27// `CortexMVariant` trait.
28pub enum CortexM7 {}
29
30impl cortexm::CortexMVariant for CortexM7 {
31    const GENERIC_ISR: unsafe extern "C" fn() = cortexv7m::generic_isr_arm_v7m;
32    const SYSTICK_HANDLER: unsafe extern "C" fn() = cortexv7m::systick_handler_arm_v7m;
33    const SVC_HANDLER: unsafe extern "C" fn() = cortexv7m::svc_handler_arm_v7m;
34    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = cortexv7m::hard_fault_handler_arm_v7m;
35
36    #[cfg(all(target_arch = "arm", target_os = "none"))]
37    unsafe fn switch_to_user(
38        user_stack: *const usize,
39        process_regs: &mut [usize; 8],
40    ) -> *const usize {
41        cortexv7m::switch_to_user_arm_v7m(user_stack, process_regs)
42    }
43
44    #[cfg(not(all(target_arch = "arm", target_os = "none")))]
45    unsafe fn switch_to_user(
46        _user_stack: *const usize,
47        _process_regs: &mut [usize; 8],
48    ) -> *const usize {
49        unimplemented!()
50    }
51
52    #[inline]
53    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
54        cortexm::print_cortexm_state(writer)
55    }
56}
57
58pub mod syscall {
59    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM7>;
60}