cortexm3/
lib.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Shared implementations for ARM Cortex-M3 MCUs.
6
7#![no_std]
8
9use core::fmt::Write;
10
11pub mod mpu {
12    use kernel::utilities::StaticRef;
13
14    pub type MPU = cortexm::mpu::MPU<8, 32>;
15
16    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
17        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
18
19    pub unsafe fn new() -> MPU {
20        MPU::new(MPU_BASE_ADDRESS)
21    }
22}
23
24pub use cortexm::initialize_ram_jump_to_main;
25pub use cortexm::interrupt_mask;
26pub use cortexm::nvic;
27pub use cortexm::scb;
28pub use cortexm::support;
29pub use cortexm::systick;
30pub use cortexm::unhandled_interrupt;
31pub use cortexm::CortexMVariant;
32
33// Enum with no variants to ensure that this type is not instantiable. It is
34// only used to pass architecture-specific constants and functions via the
35// `CortexMVariant` trait.
36pub enum CortexM3 {}
37
38impl cortexm::CortexMVariant for CortexM3 {
39    const GENERIC_ISR: unsafe extern "C" fn() = cortexv7m::generic_isr_arm_v7m;
40    const SYSTICK_HANDLER: unsafe extern "C" fn() = cortexv7m::systick_handler_arm_v7m;
41    const SVC_HANDLER: unsafe extern "C" fn() = cortexv7m::svc_handler_arm_v7m;
42    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = cortexv7m::hard_fault_handler_arm_v7m;
43
44    #[cfg(all(target_arch = "arm", target_os = "none"))]
45    unsafe fn switch_to_user(
46        user_stack: *const usize,
47        process_regs: &mut [usize; 8],
48    ) -> *const usize {
49        cortexv7m::switch_to_user_arm_v7m(user_stack, process_regs)
50    }
51
52    #[cfg(not(all(target_arch = "arm", target_os = "none")))]
53    unsafe fn switch_to_user(
54        _user_stack: *const usize,
55        _process_regs: &mut [usize; 8],
56    ) -> *const usize {
57        unimplemented!()
58    }
59
60    #[inline]
61    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
62        cortexm::print_cortexm_state(writer)
63    }
64}
65
66pub mod syscall {
67    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM3>;
68}
cortexm3/lib.rs

cortexm3/
lib.rs
