cortexm0p/
lib.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Shared implementations for ARM Cortex-M0+ MCUs.
6
7#![no_std]
8
9use core::fmt::Write;
10
11pub mod mpu {
12    use kernel::utilities::StaticRef;
13
14    pub type MPU = cortexm::mpu::MPU<8, 256>;
15
16    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
17        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
18
19    pub unsafe fn new() -> MPU {
20        MPU::new(MPU_BASE_ADDRESS)
21    }
22}
23
24// Re-export the base generic cortex-m functions here as they are
25// valid on cortex-m0.
26pub use cortexm::support;
27
28pub use cortexm::initialize_ram_jump_to_main;
29pub use cortexm::interrupt_mask;
30pub use cortexm::nvic;
31pub use cortexm::scb;
32pub use cortexm::systick;
33pub use cortexm::unhandled_interrupt;
34pub use cortexm::CortexMVariant;
35use cortexm0::CortexM0;
36
37// Mock implementation for tests on Travis-CI.
38#[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
39pub unsafe extern "C" fn svc_handler_m0p() {
40    unimplemented!()
41}
42
43#[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
44extern "C" {
45    pub fn svc_handler_m0p();
46}
47
48#[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
49core::arch::global_asm!(
50    "
51  .section .svc_handler_m0p, \"ax\"
52  .global svc_handler_m0p
53  .thumb_func
54svc_handler_m0p:
55  ldr r0, 100f // EXC_RETURN_MSP
56  cmp lr, r0
57  bne 300f // to_kernel
58
59  // If we get here, then this is a context switch from the kernel to the
60  // application. Set thread mode to unprivileged to run the application.
61  movs r0, #1
62  msr CONTROL, r0
63  ldr r1, 200f // EXC_RETURN_PSP
64  bx r1
65
66300: // to_kernel
67  ldr r0, =SYSCALL_FIRED
68  movs r1, #1
69  str r1, [r0, #0]
70  // Set thread mode to privileged as we switch back to the kernel.
71  movs r0, #0
72  msr CONTROL, r0
73  ldr r1, 100f // EXC_RETURN_MSP
74  bx r1
75
76.align 4
77100: // EXC_RETURN_MSP
78  .word 0xFFFFFFF9
79200: // EXC_RETURN_PSP
80  .word 0xFFFFFFFD
81  "
82);
83
84// Enum with no variants to ensure that this type is not instantiable. It is
85// only used to pass architecture-specific constants and functions via the
86// `CortexMVariant` trait.
87pub enum CortexM0P {}
88
89impl cortexm::CortexMVariant for CortexM0P {
90    const GENERIC_ISR: unsafe extern "C" fn() = CortexM0::GENERIC_ISR;
91    const SYSTICK_HANDLER: unsafe extern "C" fn() = CortexM0::SYSTICK_HANDLER;
92    const SVC_HANDLER: unsafe extern "C" fn() = svc_handler_m0p;
93    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = CortexM0::HARD_FAULT_HANDLER;
94
95    #[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
96    unsafe fn switch_to_user(
97        user_stack: *const usize,
98        process_regs: &mut [usize; 8],
99    ) -> *const usize {
100        CortexM0::switch_to_user(user_stack, process_regs)
101    }
102
103    #[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
104    unsafe fn switch_to_user(
105        _user_stack: *const usize,
106        _process_regs: &mut [usize; 8],
107    ) -> *const usize {
108        unimplemented!()
109    }
110
111    #[inline]
112    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
113        cortexm::print_cortexm_state(writer)
114    }
115}
116
117pub mod syscall {
118    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM0P>;
119}
cortexm0p/lib.rs

cortexm0p/
lib.rs
