cortexm0p/
lib.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Shared implementations for ARM Cortex-M0+ MCUs.
6
7#![no_std]
8
9use core::fmt::Write;
10
11pub mod mpu {
12    use kernel::utilities::StaticRef;
13
14    pub type MPU = cortexm::mpu::MPU<8, 256>;
15
16    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
17        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
18
19    pub unsafe fn new() -> MPU {
20        MPU::new(MPU_BASE_ADDRESS)
21    }
22}
23
24// Re-export the base generic cortex-m functions here as they are
25// valid on cortex-m0.
26pub use cortexm::support;
27
28pub use cortexm::initialize_ram_jump_to_main;
29pub use cortexm::interrupt_mask;
30pub use cortexm::nvic;
31pub use cortexm::scb;
32pub use cortexm::systick;
33pub use cortexm::thread_id;
34pub use cortexm::unhandled_interrupt;
35pub use cortexm::CortexMVariant;
36use cortexm0::CortexM0;
37
38// Mock implementation for tests on Travis-CI.
39#[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
40pub unsafe extern "C" fn svc_handler() {
41    unimplemented!()
42}
43
44#[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
45#[unsafe(naked)]
46pub unsafe extern "C" fn svc_handler() {
47    use core::arch::naked_asm;
48    naked_asm!(
49        "
50    ldr r0, 100f // EXC_RETURN_MSP
51    cmp lr, r0
52    bne 300f // to_kernel
53
54    // If we get here, then this is a context switch from the kernel to the
55    // application. Set thread mode to unprivileged to run the application.
56    movs r0, #1
57    msr CONTROL, r0
58    ldr r1, 200f // EXC_RETURN_PSP
59    bx r1
60
61300: // to_kernel
62    ldr r0, =SYSCALL_FIRED
63    movs r1, #1
64    str r1, [r0, #0]
65    // Set thread mode to privileged as we switch back to the kernel.
66    movs r0, #0
67    msr CONTROL, r0
68    ldr r1, 100f // EXC_RETURN_MSP
69    bx r1
70
71    .align 4
72100: // EXC_RETURN_MSP
73    .word 0xFFFFFFF9
74200: // EXC_RETURN_PSP
75    .word 0xFFFFFFFD
76        "
77    );
78}
79
80// Enum with no variants to ensure that this type is not instantiable. It is
81// only used to pass architecture-specific constants and functions via the
82// `CortexMVariant` trait.
83pub enum CortexM0P {}
84
85impl cortexm::CortexMVariant for CortexM0P {
86    const GENERIC_ISR: unsafe extern "C" fn() = CortexM0::GENERIC_ISR;
87    const SYSTICK_HANDLER: unsafe extern "C" fn() = CortexM0::SYSTICK_HANDLER;
88    const SVC_HANDLER: unsafe extern "C" fn() = svc_handler;
89    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = CortexM0::HARD_FAULT_HANDLER;
90
91    #[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
92    unsafe fn switch_to_user(
93        user_stack: *const usize,
94        process_regs: &mut [usize; 8],
95    ) -> *const usize {
96        CortexM0::switch_to_user(user_stack, process_regs)
97    }
98
99    #[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
100    unsafe fn switch_to_user(
101        _user_stack: *const usize,
102        _process_regs: &mut [usize; 8],
103    ) -> *const usize {
104        unimplemented!()
105    }
106
107    #[inline]
108    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
109        cortexm::print_cortexm_state(writer)
110    }
111}
112
113pub mod syscall {
114    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM0P>;
115}
cortexm0p/lib.rs

cortexm0p/
lib.rs
