lowrisc/registers/
entropy_src_regs.rs

Help
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for entropy_src.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/entropy_src/data/entropy_src.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const ENTROPY_SRC_PARAM_NUM_ALERTS: u32 = 2;
16/// Register width
17pub const ENTROPY_SRC_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub EntropySrcRegisters {
21        /// Interrupt State Register
22        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
23        /// Interrupt Enable Register
24        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Test Register
26        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
27        /// Alert Test Register
28        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// Register write enable for module enable register
30        (0x0010 => pub(crate) me_regwen: ReadWrite<u32, ME_REGWEN::Register>),
31        /// Register write enable for control and threshold registers
32        (0x0014 => pub(crate) sw_regupd: ReadWrite<u32, SW_REGUPD::Register>),
33        /// Register write enable for all control registers
34        (0x0018 => pub(crate) regwen: ReadWrite<u32, REGWEN::Register>),
35        /// Revision register
36        (0x001c => pub(crate) rev: ReadWrite<u32, REV::Register>),
37        /// Module enable register
38        (0x0020 => pub(crate) module_enable: ReadWrite<u32, MODULE_ENABLE::Register>),
39        /// Configuration register
40        (0x0024 => pub(crate) conf: ReadWrite<u32, CONF::Register>),
41        /// Entropy control register
42        (0x0028 => pub(crate) entropy_control: ReadWrite<u32, ENTROPY_CONTROL::Register>),
43        /// Entropy data bits
44        (0x002c => pub(crate) entropy_data: ReadWrite<u32, ENTROPY_DATA::Register>),
45        /// Health test windows register
46        (0x0030 => pub(crate) health_test_windows: ReadWrite<u32, HEALTH_TEST_WINDOWS::Register>),
47        /// Repetition count test thresholds register
48        (0x0034 => pub(crate) repcnt_thresholds: ReadWrite<u32, REPCNT_THRESHOLDS::Register>),
49        /// Repetition count symbol test thresholds register
50        (0x0038 => pub(crate) repcnts_thresholds: ReadWrite<u32, REPCNTS_THRESHOLDS::Register>),
51        /// Adaptive proportion test high thresholds register
52        (0x003c => pub(crate) adaptp_hi_thresholds: ReadWrite<u32, ADAPTP_HI_THRESHOLDS::Register>),
53        /// Adaptive proportion test low thresholds register
54        (0x0040 => pub(crate) adaptp_lo_thresholds: ReadWrite<u32, ADAPTP_LO_THRESHOLDS::Register>),
55        /// Bucket test thresholds register
56        (0x0044 => pub(crate) bucket_thresholds: ReadWrite<u32, BUCKET_THRESHOLDS::Register>),
57        /// Markov test high thresholds register
58        (0x0048 => pub(crate) markov_hi_thresholds: ReadWrite<u32, MARKOV_HI_THRESHOLDS::Register>),
59        /// Markov test low thresholds register
60        (0x004c => pub(crate) markov_lo_thresholds: ReadWrite<u32, MARKOV_LO_THRESHOLDS::Register>),
61        /// External health test high thresholds register
62        (0x0050 => pub(crate) extht_hi_thresholds: ReadWrite<u32, EXTHT_HI_THRESHOLDS::Register>),
63        /// External health test low thresholds register
64        (0x0054 => pub(crate) extht_lo_thresholds: ReadWrite<u32, EXTHT_LO_THRESHOLDS::Register>),
65        /// Repetition count test high watermarks register
66        (0x0058 => pub(crate) repcnt_hi_watermarks: ReadWrite<u32, REPCNT_HI_WATERMARKS::Register>),
67        /// Repetition count symbol test high watermarks register
68        (0x005c => pub(crate) repcnts_hi_watermarks: ReadWrite<u32, REPCNTS_HI_WATERMARKS::Register>),
69        /// Adaptive proportion test high watermarks register
70        (0x0060 => pub(crate) adaptp_hi_watermarks: ReadWrite<u32, ADAPTP_HI_WATERMARKS::Register>),
71        /// Adaptive proportion test low watermarks register
72        (0x0064 => pub(crate) adaptp_lo_watermarks: ReadWrite<u32, ADAPTP_LO_WATERMARKS::Register>),
73        /// External health test high watermarks register
74        (0x0068 => pub(crate) extht_hi_watermarks: ReadWrite<u32, EXTHT_HI_WATERMARKS::Register>),
75        /// External health test low watermarks register
76        (0x006c => pub(crate) extht_lo_watermarks: ReadWrite<u32, EXTHT_LO_WATERMARKS::Register>),
77        /// Bucket test high watermarks register
78        (0x0070 => pub(crate) bucket_hi_watermarks: ReadWrite<u32, BUCKET_HI_WATERMARKS::Register>),
79        /// Markov test high watermarks register
80        (0x0074 => pub(crate) markov_hi_watermarks: ReadWrite<u32, MARKOV_HI_WATERMARKS::Register>),
81        /// Markov test low watermarks register
82        (0x0078 => pub(crate) markov_lo_watermarks: ReadWrite<u32, MARKOV_LO_WATERMARKS::Register>),
83        /// Repetition count test failure counter register
84        (0x007c => pub(crate) repcnt_total_fails: ReadWrite<u32, REPCNT_TOTAL_FAILS::Register>),
85        /// Repetition count symbol test failure counter register
86        (0x0080 => pub(crate) repcnts_total_fails: ReadWrite<u32, REPCNTS_TOTAL_FAILS::Register>),
87        /// Adaptive proportion high test failure counter register
88        (0x0084 => pub(crate) adaptp_hi_total_fails: ReadWrite<u32, ADAPTP_HI_TOTAL_FAILS::Register>),
89        /// Adaptive proportion low test failure counter register
90        (0x0088 => pub(crate) adaptp_lo_total_fails: ReadWrite<u32, ADAPTP_LO_TOTAL_FAILS::Register>),
91        /// Bucket test failure counter register
92        (0x008c => pub(crate) bucket_total_fails: ReadWrite<u32, BUCKET_TOTAL_FAILS::Register>),
93        /// Markov high test failure counter register
94        (0x0090 => pub(crate) markov_hi_total_fails: ReadWrite<u32, MARKOV_HI_TOTAL_FAILS::Register>),
95        /// Markov low test failure counter register
96        (0x0094 => pub(crate) markov_lo_total_fails: ReadWrite<u32, MARKOV_LO_TOTAL_FAILS::Register>),
97        /// External health test high threshold failure counter register
98        (0x0098 => pub(crate) extht_hi_total_fails: ReadWrite<u32, EXTHT_HI_TOTAL_FAILS::Register>),
99        /// External health test low threshold failure counter register
100        (0x009c => pub(crate) extht_lo_total_fails: ReadWrite<u32, EXTHT_LO_TOTAL_FAILS::Register>),
101        /// Alert threshold register
102        (0x00a0 => pub(crate) alert_threshold: ReadWrite<u32, ALERT_THRESHOLD::Register>),
103        /// Alert summary failure counts register
104        (0x00a4 => pub(crate) alert_summary_fail_counts: ReadWrite<u32, ALERT_SUMMARY_FAIL_COUNTS::Register>),
105        /// Alert failure counts register
106        (0x00a8 => pub(crate) alert_fail_counts: ReadWrite<u32, ALERT_FAIL_COUNTS::Register>),
107        /// External health test alert failure counts register
108        (0x00ac => pub(crate) extht_fail_counts: ReadWrite<u32, EXTHT_FAIL_COUNTS::Register>),
109        /// Firmware override control register
110        (0x00b0 => pub(crate) fw_ov_control: ReadWrite<u32, FW_OV_CONTROL::Register>),
111        /// Firmware override sha3 block start control register
112        (0x00b4 => pub(crate) fw_ov_sha3_start: ReadWrite<u32, FW_OV_SHA3_START::Register>),
113        /// Firmware override FIFO write full status register
114        (0x00b8 => pub(crate) fw_ov_wr_fifo_full: ReadWrite<u32, FW_OV_WR_FIFO_FULL::Register>),
115        /// Firmware override observe FIFO overflow status
116        (0x00bc => pub(crate) fw_ov_rd_fifo_overflow: ReadWrite<u32, FW_OV_RD_FIFO_OVERFLOW::Register>),
117        /// Firmware override observe FIFO read register
118        (0x00c0 => pub(crate) fw_ov_rd_data: ReadWrite<u32, FW_OV_RD_DATA::Register>),
119        /// Firmware override FIFO write register
120        (0x00c4 => pub(crate) fw_ov_wr_data: ReadWrite<u32, FW_OV_WR_DATA::Register>),
121        /// Observe FIFO threshold register
122        (0x00c8 => pub(crate) observe_fifo_thresh: ReadWrite<u32, OBSERVE_FIFO_THRESH::Register>),
123        /// Observe FIFO depth register
124        (0x00cc => pub(crate) observe_fifo_depth: ReadWrite<u32, OBSERVE_FIFO_DEPTH::Register>),
125        /// Debug status register
126        (0x00d0 => pub(crate) debug_status: ReadWrite<u32, DEBUG_STATUS::Register>),
127        /// Recoverable alert status register
128        (0x00d4 => pub(crate) recov_alert_sts: ReadWrite<u32, RECOV_ALERT_STS::Register>),
129        /// Hardware detection of error conditions status register
130        (0x00d8 => pub(crate) err_code: ReadWrite<u32, ERR_CODE::Register>),
131        /// Test error conditions register
132        (0x00dc => pub(crate) err_code_test: ReadWrite<u32, ERR_CODE_TEST::Register>),
133        /// Main state machine state debug register
134        (0x00e0 => pub(crate) main_sm_state: ReadWrite<u32, MAIN_SM_STATE::Register>),
135        (0x00e4 => @END),
136    }
137}
138
139register_bitfields![u32,
140    /// Common Interrupt Offsets
141    pub(crate) INTR [
142        ES_ENTROPY_VALID OFFSET(0) NUMBITS(1) [],
143        ES_HEALTH_TEST_FAILED OFFSET(1) NUMBITS(1) [],
144        ES_OBSERVE_FIFO_READY OFFSET(2) NUMBITS(1) [],
145        ES_FATAL_ERR OFFSET(3) NUMBITS(1) [],
146    ],
147    pub(crate) ALERT_TEST [
148        RECOV_ALERT OFFSET(0) NUMBITS(1) [],
149        FATAL_ALERT OFFSET(1) NUMBITS(1) [],
150    ],
151    pub(crate) ME_REGWEN [
152        ME_REGWEN OFFSET(0) NUMBITS(1) [],
153    ],
154    pub(crate) SW_REGUPD [
155        SW_REGUPD OFFSET(0) NUMBITS(1) [],
156    ],
157    pub(crate) REGWEN [
158        REGWEN OFFSET(0) NUMBITS(1) [],
159    ],
160    pub(crate) REV [
161        ABI_REVISION OFFSET(0) NUMBITS(8) [],
162        HW_REVISION OFFSET(8) NUMBITS(8) [],
163        CHIP_TYPE OFFSET(16) NUMBITS(8) [],
164    ],
165    pub(crate) MODULE_ENABLE [
166        MODULE_ENABLE OFFSET(0) NUMBITS(4) [],
167    ],
168    pub(crate) CONF [
169        FIPS_ENABLE OFFSET(0) NUMBITS(4) [],
170        ENTROPY_DATA_REG_ENABLE OFFSET(4) NUMBITS(4) [],
171        THRESHOLD_SCOPE OFFSET(12) NUMBITS(4) [],
172        RNG_BIT_ENABLE OFFSET(20) NUMBITS(4) [],
173        RNG_BIT_SEL OFFSET(24) NUMBITS(2) [],
174    ],
175    pub(crate) ENTROPY_CONTROL [
176        ES_ROUTE OFFSET(0) NUMBITS(4) [],
177        ES_TYPE OFFSET(4) NUMBITS(4) [],
178    ],
179    pub(crate) ENTROPY_DATA [
180        ENTROPY_DATA OFFSET(0) NUMBITS(32) [],
181    ],
182    pub(crate) HEALTH_TEST_WINDOWS [
183        FIPS_WINDOW OFFSET(0) NUMBITS(16) [],
184        BYPASS_WINDOW OFFSET(16) NUMBITS(16) [],
185    ],
186    pub(crate) REPCNT_THRESHOLDS [
187        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
188        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
189    ],
190    pub(crate) REPCNTS_THRESHOLDS [
191        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
192        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
193    ],
194    pub(crate) ADAPTP_HI_THRESHOLDS [
195        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
196        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
197    ],
198    pub(crate) ADAPTP_LO_THRESHOLDS [
199        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
200        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
201    ],
202    pub(crate) BUCKET_THRESHOLDS [
203        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
204        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
205    ],
206    pub(crate) MARKOV_HI_THRESHOLDS [
207        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
208        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
209    ],
210    pub(crate) MARKOV_LO_THRESHOLDS [
211        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
212        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
213    ],
214    pub(crate) EXTHT_HI_THRESHOLDS [
215        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
216        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
217    ],
218    pub(crate) EXTHT_LO_THRESHOLDS [
219        FIPS_THRESH OFFSET(0) NUMBITS(16) [],
220        BYPASS_THRESH OFFSET(16) NUMBITS(16) [],
221    ],
222    pub(crate) REPCNT_HI_WATERMARKS [
223        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
224        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
225    ],
226    pub(crate) REPCNTS_HI_WATERMARKS [
227        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
228        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
229    ],
230    pub(crate) ADAPTP_HI_WATERMARKS [
231        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
232        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
233    ],
234    pub(crate) ADAPTP_LO_WATERMARKS [
235        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
236        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
237    ],
238    pub(crate) EXTHT_HI_WATERMARKS [
239        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
240        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
241    ],
242    pub(crate) EXTHT_LO_WATERMARKS [
243        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
244        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
245    ],
246    pub(crate) BUCKET_HI_WATERMARKS [
247        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
248        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
249    ],
250    pub(crate) MARKOV_HI_WATERMARKS [
251        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
252        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
253    ],
254    pub(crate) MARKOV_LO_WATERMARKS [
255        FIPS_WATERMARK OFFSET(0) NUMBITS(16) [],
256        BYPASS_WATERMARK OFFSET(16) NUMBITS(16) [],
257    ],
258    pub(crate) REPCNT_TOTAL_FAILS [
259        REPCNT_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
260    ],
261    pub(crate) REPCNTS_TOTAL_FAILS [
262        REPCNTS_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
263    ],
264    pub(crate) ADAPTP_HI_TOTAL_FAILS [
265        ADAPTP_HI_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
266    ],
267    pub(crate) ADAPTP_LO_TOTAL_FAILS [
268        ADAPTP_LO_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
269    ],
270    pub(crate) BUCKET_TOTAL_FAILS [
271        BUCKET_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
272    ],
273    pub(crate) MARKOV_HI_TOTAL_FAILS [
274        MARKOV_HI_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
275    ],
276    pub(crate) MARKOV_LO_TOTAL_FAILS [
277        MARKOV_LO_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
278    ],
279    pub(crate) EXTHT_HI_TOTAL_FAILS [
280        EXTHT_HI_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
281    ],
282    pub(crate) EXTHT_LO_TOTAL_FAILS [
283        EXTHT_LO_TOTAL_FAILS OFFSET(0) NUMBITS(32) [],
284    ],
285    pub(crate) ALERT_THRESHOLD [
286        ALERT_THRESHOLD OFFSET(0) NUMBITS(16) [],
287        ALERT_THRESHOLD_INV OFFSET(16) NUMBITS(16) [],
288    ],
289    pub(crate) ALERT_SUMMARY_FAIL_COUNTS [
290        ANY_FAIL_COUNT OFFSET(0) NUMBITS(16) [],
291    ],
292    pub(crate) ALERT_FAIL_COUNTS [
293        REPCNT_FAIL_COUNT OFFSET(4) NUMBITS(4) [],
294        ADAPTP_HI_FAIL_COUNT OFFSET(8) NUMBITS(4) [],
295        ADAPTP_LO_FAIL_COUNT OFFSET(12) NUMBITS(4) [],
296        BUCKET_FAIL_COUNT OFFSET(16) NUMBITS(4) [],
297        MARKOV_HI_FAIL_COUNT OFFSET(20) NUMBITS(4) [],
298        MARKOV_LO_FAIL_COUNT OFFSET(24) NUMBITS(4) [],
299        REPCNTS_FAIL_COUNT OFFSET(28) NUMBITS(4) [],
300    ],
301    pub(crate) EXTHT_FAIL_COUNTS [
302        EXTHT_HI_FAIL_COUNT OFFSET(0) NUMBITS(4) [],
303        EXTHT_LO_FAIL_COUNT OFFSET(4) NUMBITS(4) [],
304    ],
305    pub(crate) FW_OV_CONTROL [
306        FW_OV_MODE OFFSET(0) NUMBITS(4) [],
307        FW_OV_ENTROPY_INSERT OFFSET(4) NUMBITS(4) [],
308    ],
309    pub(crate) FW_OV_SHA3_START [
310        FW_OV_INSERT_START OFFSET(0) NUMBITS(4) [],
311    ],
312    pub(crate) FW_OV_WR_FIFO_FULL [
313        FW_OV_WR_FIFO_FULL OFFSET(0) NUMBITS(1) [],
314    ],
315    pub(crate) FW_OV_RD_FIFO_OVERFLOW [
316        FW_OV_RD_FIFO_OVERFLOW OFFSET(0) NUMBITS(1) [],
317    ],
318    pub(crate) FW_OV_RD_DATA [
319        FW_OV_RD_DATA OFFSET(0) NUMBITS(32) [],
320    ],
321    pub(crate) FW_OV_WR_DATA [
322        FW_OV_WR_DATA OFFSET(0) NUMBITS(32) [],
323    ],
324    pub(crate) OBSERVE_FIFO_THRESH [
325        OBSERVE_FIFO_THRESH OFFSET(0) NUMBITS(7) [],
326    ],
327    pub(crate) OBSERVE_FIFO_DEPTH [
328        OBSERVE_FIFO_DEPTH OFFSET(0) NUMBITS(7) [],
329    ],
330    pub(crate) DEBUG_STATUS [
331        ENTROPY_FIFO_DEPTH OFFSET(0) NUMBITS(3) [],
332        SHA3_FSM OFFSET(3) NUMBITS(3) [],
333        SHA3_BLOCK_PR OFFSET(6) NUMBITS(1) [],
334        SHA3_SQUEEZING OFFSET(7) NUMBITS(1) [],
335        SHA3_ABSORBED OFFSET(8) NUMBITS(1) [],
336        SHA3_ERR OFFSET(9) NUMBITS(1) [],
337        MAIN_SM_IDLE OFFSET(16) NUMBITS(1) [],
338        MAIN_SM_BOOT_DONE OFFSET(17) NUMBITS(1) [],
339    ],
340    pub(crate) RECOV_ALERT_STS [
341        FIPS_ENABLE_FIELD_ALERT OFFSET(0) NUMBITS(1) [],
342        ENTROPY_DATA_REG_EN_FIELD_ALERT OFFSET(1) NUMBITS(1) [],
343        MODULE_ENABLE_FIELD_ALERT OFFSET(2) NUMBITS(1) [],
344        THRESHOLD_SCOPE_FIELD_ALERT OFFSET(3) NUMBITS(1) [],
345        RNG_BIT_ENABLE_FIELD_ALERT OFFSET(5) NUMBITS(1) [],
346        FW_OV_SHA3_START_FIELD_ALERT OFFSET(7) NUMBITS(1) [],
347        FW_OV_MODE_FIELD_ALERT OFFSET(8) NUMBITS(1) [],
348        FW_OV_ENTROPY_INSERT_FIELD_ALERT OFFSET(9) NUMBITS(1) [],
349        ES_ROUTE_FIELD_ALERT OFFSET(10) NUMBITS(1) [],
350        ES_TYPE_FIELD_ALERT OFFSET(11) NUMBITS(1) [],
351        ES_MAIN_SM_ALERT OFFSET(12) NUMBITS(1) [],
352        ES_BUS_CMP_ALERT OFFSET(13) NUMBITS(1) [],
353        ES_THRESH_CFG_ALERT OFFSET(14) NUMBITS(1) [],
354        ES_FW_OV_WR_ALERT OFFSET(15) NUMBITS(1) [],
355        ES_FW_OV_DISABLE_ALERT OFFSET(16) NUMBITS(1) [],
356    ],
357    pub(crate) ERR_CODE [
358        SFIFO_ESRNG_ERR OFFSET(0) NUMBITS(1) [],
359        SFIFO_OBSERVE_ERR OFFSET(1) NUMBITS(1) [],
360        SFIFO_ESFINAL_ERR OFFSET(2) NUMBITS(1) [],
361        ES_ACK_SM_ERR OFFSET(20) NUMBITS(1) [],
362        ES_MAIN_SM_ERR OFFSET(21) NUMBITS(1) [],
363        ES_CNTR_ERR OFFSET(22) NUMBITS(1) [],
364        SHA3_STATE_ERR OFFSET(23) NUMBITS(1) [],
365        SHA3_RST_STORAGE_ERR OFFSET(24) NUMBITS(1) [],
366        FIFO_WRITE_ERR OFFSET(28) NUMBITS(1) [],
367        FIFO_READ_ERR OFFSET(29) NUMBITS(1) [],
368        FIFO_STATE_ERR OFFSET(30) NUMBITS(1) [],
369    ],
370    pub(crate) ERR_CODE_TEST [
371        ERR_CODE_TEST OFFSET(0) NUMBITS(5) [],
372    ],
373    pub(crate) MAIN_SM_STATE [
374        MAIN_SM_STATE OFFSET(0) NUMBITS(9) [],
375    ],
376];
377
378// End generated register constants for entropy_src
lowrisc/registers/entropy_src_regs.rs

lowrisc/registers/
entropy_src_regs.rs
