lowrisc/registers/
rv_core_ibex_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for rv_core_ibex.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of software triggerable alerts
15pub const RV_CORE_IBEX_PARAM_NUM_SW_ALERTS: u32 = 2;
16/// Number of translatable regions per ibex bus
17pub const RV_CORE_IBEX_PARAM_NUM_REGIONS: u32 = 2;
18/// Number of scratch words maintained.
19pub const RV_CORE_IBEX_PARAM_NUM_SCRATCH_WORDS: u32 = 8;
20/// Number of alerts
21pub const RV_CORE_IBEX_PARAM_NUM_ALERTS: u32 = 4;
22/// Register width
23pub const RV_CORE_IBEX_PARAM_REG_WIDTH: u32 = 32;
24
25register_structs! {
26    pub RvCoreIbexRegisters {
27        /// Alert Test Register
28        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// Software recoverable error
30        (0x0004 => pub(crate) sw_recov_err: ReadWrite<u32, SW_RECOV_ERR::Register>),
31        /// Software fatal error
32        (0x0008 => pub(crate) sw_fatal_err: ReadWrite<u32, SW_FATAL_ERR::Register>),
33        /// Ibus address control regwen.
34        (0x000c => pub(crate) ibus_regwen: [ReadWrite<u32, IBUS_REGWEN::Register>; 2]),
35        ///   Enable Ibus address matching
36        (0x0014 => pub(crate) ibus_addr_en: [ReadWrite<u32, IBUS_ADDR_EN::Register>; 2]),
37        ///   Matching region programming for ibus.
38        (0x001c => pub(crate) ibus_addr_matching: [ReadWrite<u32, IBUS_ADDR_MATCHING::Register>; 2]),
39        ///   The remap address after a match has been made.
40        (0x0024 => pub(crate) ibus_remap_addr: [ReadWrite<u32, IBUS_REMAP_ADDR::Register>; 2]),
41        /// Dbus address control regwen.
42        (0x002c => pub(crate) dbus_regwen: [ReadWrite<u32, DBUS_REGWEN::Register>; 2]),
43        ///   Enable dbus address matching
44        (0x0034 => pub(crate) dbus_addr_en: [ReadWrite<u32, DBUS_ADDR_EN::Register>; 2]),
45        ///   See !!IBUS_ADDR_MATCHING_0 for detailed description.
46        (0x003c => pub(crate) dbus_addr_matching: [ReadWrite<u32, DBUS_ADDR_MATCHING::Register>; 2]),
47        ///   See !!IBUS_REMAP_ADDR_0 for a detailed description.
48        (0x0044 => pub(crate) dbus_remap_addr: [ReadWrite<u32, DBUS_REMAP_ADDR::Register>; 2]),
49        /// Enable mask for NMI.
50        (0x004c => pub(crate) nmi_enable: ReadWrite<u32, NMI_ENABLE::Register>),
51        /// Current NMI state
52        (0x0050 => pub(crate) nmi_state: ReadWrite<u32, NMI_STATE::Register>),
53        /// error status
54        (0x0054 => pub(crate) err_status: ReadWrite<u32, ERR_STATUS::Register>),
55        /// Random data from EDN
56        (0x0058 => pub(crate) rnd_data: ReadWrite<u32, RND_DATA::Register>),
57        /// Status of random data in !!RND_DATA
58        (0x005c => pub(crate) rnd_status: ReadWrite<u32, RND_STATUS::Register>),
59        /// FPGA build timestamp info.
60        (0x0060 => pub(crate) fpga_info: ReadWrite<u32, FPGA_INFO::Register>),
61        (0x0064 => _reserved1),
62        /// Memory area: Exposed tlul window for DV only purposes.
63        (0x0080 => pub(crate) dv_sim_window: [ReadWrite<u32>; 8]),
64        (0x00a0 => @END),
65    }
66}
67
68register_bitfields![u32,
69    pub(crate) ALERT_TEST [
70        FATAL_SW_ERR OFFSET(0) NUMBITS(1) [],
71        RECOV_SW_ERR OFFSET(1) NUMBITS(1) [],
72        FATAL_HW_ERR OFFSET(2) NUMBITS(1) [],
73        RECOV_HW_ERR OFFSET(3) NUMBITS(1) [],
74    ],
75    pub(crate) SW_RECOV_ERR [
76        VAL OFFSET(0) NUMBITS(4) [],
77    ],
78    pub(crate) SW_FATAL_ERR [
79        VAL OFFSET(0) NUMBITS(4) [],
80    ],
81    pub(crate) IBUS_REGWEN [
82        EN_0 OFFSET(0) NUMBITS(1) [
83            LOCKED = 0,
84            ENABLED = 1,
85        ],
86    ],
87    pub(crate) IBUS_ADDR_EN [
88        EN_0 OFFSET(0) NUMBITS(1) [],
89    ],
90    pub(crate) IBUS_ADDR_MATCHING [
91        VAL_0 OFFSET(0) NUMBITS(32) [],
92    ],
93    pub(crate) IBUS_REMAP_ADDR [
94        VAL_0 OFFSET(0) NUMBITS(32) [],
95    ],
96    pub(crate) DBUS_REGWEN [
97        EN_0 OFFSET(0) NUMBITS(1) [
98            LOCKED = 0,
99            ENABLED = 1,
100        ],
101    ],
102    pub(crate) DBUS_ADDR_EN [
103        EN_0 OFFSET(0) NUMBITS(1) [],
104    ],
105    pub(crate) DBUS_ADDR_MATCHING [
106        VAL_0 OFFSET(0) NUMBITS(32) [],
107    ],
108    pub(crate) DBUS_REMAP_ADDR [
109        VAL_0 OFFSET(0) NUMBITS(32) [],
110    ],
111    pub(crate) NMI_ENABLE [
112        ALERT_EN OFFSET(0) NUMBITS(1) [],
113        WDOG_EN OFFSET(1) NUMBITS(1) [],
114    ],
115    pub(crate) NMI_STATE [
116        ALERT OFFSET(0) NUMBITS(1) [],
117        WDOG OFFSET(1) NUMBITS(1) [],
118    ],
119    pub(crate) ERR_STATUS [
120        REG_INTG_ERR OFFSET(0) NUMBITS(1) [],
121        FATAL_INTG_ERR OFFSET(8) NUMBITS(1) [],
122        FATAL_CORE_ERR OFFSET(9) NUMBITS(1) [],
123        RECOV_CORE_ERR OFFSET(10) NUMBITS(1) [],
124    ],
125    pub(crate) RND_DATA [
126        DATA OFFSET(0) NUMBITS(32) [],
127    ],
128    pub(crate) RND_STATUS [
129        RND_DATA_VALID OFFSET(0) NUMBITS(1) [],
130        RND_DATA_FIPS OFFSET(1) NUMBITS(1) [],
131    ],
132    pub(crate) FPGA_INFO [
133        VAL OFFSET(0) NUMBITS(32) [],
134    ],
135];
136
137// End generated register constants for rv_core_ibex
lowrisc/registers/rv_core_ibex_regs.rs

lowrisc/registers/
rv_core_ibex_regs.rs
