lowrisc/registers/
usbdev_regs.rs

Help
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for usbdev.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/usbdev/data/usbdev.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of endpoints
15pub const USBDEV_PARAM_N_ENDPOINTS: u32 = 12;
16/// Number of alerts
17pub const USBDEV_PARAM_NUM_ALERTS: u32 = 1;
18/// Register width
19pub const USBDEV_PARAM_REG_WIDTH: u32 = 32;
20
21register_structs! {
22    pub UsbdevRegisters {
23        /// Interrupt State Register
24        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Enable Register
26        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
27        /// Interrupt Test Register
28        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
29        /// Alert Test Register
30        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
31        /// USB Control
32        (0x0010 => pub(crate) usbctrl: ReadWrite<u32, USBCTRL::Register>),
33        /// Enable an endpoint to respond to transactions in the downstream direction.
34        (0x0014 => pub(crate) ep_out_enable: [ReadWrite<u32, EP_OUT_ENABLE::Register>; 1]),
35        /// Enable an endpoint to respond to transactions in the upstream direction.
36        (0x0018 => pub(crate) ep_in_enable: [ReadWrite<u32, EP_IN_ENABLE::Register>; 1]),
37        /// USB Status
38        (0x001c => pub(crate) usbstat: ReadWrite<u32, USBSTAT::Register>),
39        /// Available Buffer FIFO
40        (0x0020 => pub(crate) avbuffer: ReadWrite<u32, AVBUFFER::Register>),
41        /// Received Buffer FIFO
42        (0x0024 => pub(crate) rxfifo: ReadWrite<u32, RXFIFO::Register>),
43        /// Receive SETUP transaction enable
44        (0x0028 => pub(crate) rxenable_setup: [ReadWrite<u32, RXENABLE_SETUP::Register>; 1]),
45        /// Receive OUT transaction enable
46        (0x002c => pub(crate) rxenable_out: [ReadWrite<u32, RXENABLE_OUT::Register>; 1]),
47        /// Set NAK after OUT transactions
48        (0x0030 => pub(crate) set_nak_out: [ReadWrite<u32, SET_NAK_OUT::Register>; 1]),
49        /// IN Transaction Sent
50        (0x0034 => pub(crate) in_sent: [ReadWrite<u32, IN_SENT::Register>; 1]),
51        /// OUT Endpoint STALL control
52        (0x0038 => pub(crate) out_stall: [ReadWrite<u32, OUT_STALL::Register>; 1]),
53        /// IN Endpoint STALL control
54        (0x003c => pub(crate) in_stall: [ReadWrite<u32, IN_STALL::Register>; 1]),
55        /// Configure IN Transaction
56        (0x0040 => pub(crate) configin: [ReadWrite<u32, CONFIGIN::Register>; 12]),
57        /// OUT Endpoint isochronous setting
58        (0x0070 => pub(crate) out_iso: [ReadWrite<u32, OUT_ISO::Register>; 1]),
59        /// IN Endpoint isochronous setting
60        (0x0074 => pub(crate) in_iso: [ReadWrite<u32, IN_ISO::Register>; 1]),
61        /// Clear the data toggle flag
62        (0x0078 => pub(crate) data_toggle_clear: [ReadWrite<u32, DATA_TOGGLE_CLEAR::Register>; 1]),
63        /// USB PHY pins sense.
64        (0x007c => pub(crate) phy_pins_sense: ReadWrite<u32, PHY_PINS_SENSE::Register>),
65        /// USB PHY pins drive.
66        (0x0080 => pub(crate) phy_pins_drive: ReadWrite<u32, PHY_PINS_DRIVE::Register>),
67        /// USB PHY Configuration
68        (0x0084 => pub(crate) phy_config: ReadWrite<u32, PHY_CONFIG::Register>),
69        /// USB wake module control for suspend / resume
70        (0x0088 => pub(crate) wake_control: ReadWrite<u32, WAKE_CONTROL::Register>),
71        /// USB wake module events and debug
72        (0x008c => pub(crate) wake_events: ReadWrite<u32, WAKE_EVENTS::Register>),
73        (0x0090 => _reserved1),
74        /// Memory area: 2 kB packet buffer. Divided into 32 64-byte buffers.
75        (0x0800 => pub(crate) buffer: [ReadWrite<u32>; 512]),
76        (0x1000 => @END),
77    }
78}
79
80register_bitfields![u32,
81    /// Common Interrupt Offsets
82    pub(crate) INTR [
83        PKT_RECEIVED OFFSET(0) NUMBITS(1) [],
84        PKT_SENT OFFSET(1) NUMBITS(1) [],
85        DISCONNECTED OFFSET(2) NUMBITS(1) [],
86        HOST_LOST OFFSET(3) NUMBITS(1) [],
87        LINK_RESET OFFSET(4) NUMBITS(1) [],
88        LINK_SUSPEND OFFSET(5) NUMBITS(1) [],
89        LINK_RESUME OFFSET(6) NUMBITS(1) [],
90        AV_EMPTY OFFSET(7) NUMBITS(1) [],
91        RX_FULL OFFSET(8) NUMBITS(1) [],
92        AV_OVERFLOW OFFSET(9) NUMBITS(1) [],
93        LINK_IN_ERR OFFSET(10) NUMBITS(1) [],
94        RX_CRC_ERR OFFSET(11) NUMBITS(1) [],
95        RX_PID_ERR OFFSET(12) NUMBITS(1) [],
96        RX_BITSTUFF_ERR OFFSET(13) NUMBITS(1) [],
97        FRAME OFFSET(14) NUMBITS(1) [],
98        POWERED OFFSET(15) NUMBITS(1) [],
99        LINK_OUT_ERR OFFSET(16) NUMBITS(1) [],
100    ],
101    pub(crate) ALERT_TEST [
102        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
103    ],
104    pub(crate) USBCTRL [
105        ENABLE OFFSET(0) NUMBITS(1) [],
106        RESUME_LINK_ACTIVE OFFSET(1) NUMBITS(1) [],
107        DEVICE_ADDRESS OFFSET(16) NUMBITS(7) [],
108    ],
109    pub(crate) EP_OUT_ENABLE [
110        ENABLE_0 OFFSET(0) NUMBITS(1) [],
111        ENABLE_1 OFFSET(1) NUMBITS(1) [],
112        ENABLE_2 OFFSET(2) NUMBITS(1) [],
113        ENABLE_3 OFFSET(3) NUMBITS(1) [],
114        ENABLE_4 OFFSET(4) NUMBITS(1) [],
115        ENABLE_5 OFFSET(5) NUMBITS(1) [],
116        ENABLE_6 OFFSET(6) NUMBITS(1) [],
117        ENABLE_7 OFFSET(7) NUMBITS(1) [],
118        ENABLE_8 OFFSET(8) NUMBITS(1) [],
119        ENABLE_9 OFFSET(9) NUMBITS(1) [],
120        ENABLE_10 OFFSET(10) NUMBITS(1) [],
121        ENABLE_11 OFFSET(11) NUMBITS(1) [],
122    ],
123    pub(crate) EP_IN_ENABLE [
124        ENABLE_0 OFFSET(0) NUMBITS(1) [],
125        ENABLE_1 OFFSET(1) NUMBITS(1) [],
126        ENABLE_2 OFFSET(2) NUMBITS(1) [],
127        ENABLE_3 OFFSET(3) NUMBITS(1) [],
128        ENABLE_4 OFFSET(4) NUMBITS(1) [],
129        ENABLE_5 OFFSET(5) NUMBITS(1) [],
130        ENABLE_6 OFFSET(6) NUMBITS(1) [],
131        ENABLE_7 OFFSET(7) NUMBITS(1) [],
132        ENABLE_8 OFFSET(8) NUMBITS(1) [],
133        ENABLE_9 OFFSET(9) NUMBITS(1) [],
134        ENABLE_10 OFFSET(10) NUMBITS(1) [],
135        ENABLE_11 OFFSET(11) NUMBITS(1) [],
136    ],
137    pub(crate) USBSTAT [
138        FRAME OFFSET(0) NUMBITS(11) [],
139        HOST_LOST OFFSET(11) NUMBITS(1) [],
140        LINK_STATE OFFSET(12) NUMBITS(3) [
141            DISCONNECTED = 0,
142            POWERED = 1,
143            POWERED_SUSPENDED = 2,
144            ACTIVE = 3,
145            SUSPENDED = 4,
146            ACTIVE_NOSOF = 5,
147            RESUMING = 6,
148        ],
149        SENSE OFFSET(15) NUMBITS(1) [],
150        AV_DEPTH OFFSET(16) NUMBITS(4) [],
151        AV_FULL OFFSET(23) NUMBITS(1) [],
152        RX_DEPTH OFFSET(24) NUMBITS(4) [],
153        RX_EMPTY OFFSET(31) NUMBITS(1) [],
154    ],
155    pub(crate) AVBUFFER [
156        BUFFER OFFSET(0) NUMBITS(5) [],
157    ],
158    pub(crate) RXFIFO [
159        BUFFER OFFSET(0) NUMBITS(5) [],
160        SIZE OFFSET(8) NUMBITS(7) [],
161        SETUP OFFSET(19) NUMBITS(1) [],
162        EP OFFSET(20) NUMBITS(4) [],
163    ],
164    pub(crate) RXENABLE_SETUP [
165        SETUP_0 OFFSET(0) NUMBITS(1) [],
166        SETUP_1 OFFSET(1) NUMBITS(1) [],
167        SETUP_2 OFFSET(2) NUMBITS(1) [],
168        SETUP_3 OFFSET(3) NUMBITS(1) [],
169        SETUP_4 OFFSET(4) NUMBITS(1) [],
170        SETUP_5 OFFSET(5) NUMBITS(1) [],
171        SETUP_6 OFFSET(6) NUMBITS(1) [],
172        SETUP_7 OFFSET(7) NUMBITS(1) [],
173        SETUP_8 OFFSET(8) NUMBITS(1) [],
174        SETUP_9 OFFSET(9) NUMBITS(1) [],
175        SETUP_10 OFFSET(10) NUMBITS(1) [],
176        SETUP_11 OFFSET(11) NUMBITS(1) [],
177    ],
178    pub(crate) RXENABLE_OUT [
179        OUT_0 OFFSET(0) NUMBITS(1) [],
180        OUT_1 OFFSET(1) NUMBITS(1) [],
181        OUT_2 OFFSET(2) NUMBITS(1) [],
182        OUT_3 OFFSET(3) NUMBITS(1) [],
183        OUT_4 OFFSET(4) NUMBITS(1) [],
184        OUT_5 OFFSET(5) NUMBITS(1) [],
185        OUT_6 OFFSET(6) NUMBITS(1) [],
186        OUT_7 OFFSET(7) NUMBITS(1) [],
187        OUT_8 OFFSET(8) NUMBITS(1) [],
188        OUT_9 OFFSET(9) NUMBITS(1) [],
189        OUT_10 OFFSET(10) NUMBITS(1) [],
190        OUT_11 OFFSET(11) NUMBITS(1) [],
191    ],
192    pub(crate) SET_NAK_OUT [
193        ENABLE_0 OFFSET(0) NUMBITS(1) [],
194        ENABLE_1 OFFSET(1) NUMBITS(1) [],
195        ENABLE_2 OFFSET(2) NUMBITS(1) [],
196        ENABLE_3 OFFSET(3) NUMBITS(1) [],
197        ENABLE_4 OFFSET(4) NUMBITS(1) [],
198        ENABLE_5 OFFSET(5) NUMBITS(1) [],
199        ENABLE_6 OFFSET(6) NUMBITS(1) [],
200        ENABLE_7 OFFSET(7) NUMBITS(1) [],
201        ENABLE_8 OFFSET(8) NUMBITS(1) [],
202        ENABLE_9 OFFSET(9) NUMBITS(1) [],
203        ENABLE_10 OFFSET(10) NUMBITS(1) [],
204        ENABLE_11 OFFSET(11) NUMBITS(1) [],
205    ],
206    pub(crate) IN_SENT [
207        SENT_0 OFFSET(0) NUMBITS(1) [],
208        SENT_1 OFFSET(1) NUMBITS(1) [],
209        SENT_2 OFFSET(2) NUMBITS(1) [],
210        SENT_3 OFFSET(3) NUMBITS(1) [],
211        SENT_4 OFFSET(4) NUMBITS(1) [],
212        SENT_5 OFFSET(5) NUMBITS(1) [],
213        SENT_6 OFFSET(6) NUMBITS(1) [],
214        SENT_7 OFFSET(7) NUMBITS(1) [],
215        SENT_8 OFFSET(8) NUMBITS(1) [],
216        SENT_9 OFFSET(9) NUMBITS(1) [],
217        SENT_10 OFFSET(10) NUMBITS(1) [],
218        SENT_11 OFFSET(11) NUMBITS(1) [],
219    ],
220    pub(crate) OUT_STALL [
221        ENDPOINT_0 OFFSET(0) NUMBITS(1) [],
222        ENDPOINT_1 OFFSET(1) NUMBITS(1) [],
223        ENDPOINT_2 OFFSET(2) NUMBITS(1) [],
224        ENDPOINT_3 OFFSET(3) NUMBITS(1) [],
225        ENDPOINT_4 OFFSET(4) NUMBITS(1) [],
226        ENDPOINT_5 OFFSET(5) NUMBITS(1) [],
227        ENDPOINT_6 OFFSET(6) NUMBITS(1) [],
228        ENDPOINT_7 OFFSET(7) NUMBITS(1) [],
229        ENDPOINT_8 OFFSET(8) NUMBITS(1) [],
230        ENDPOINT_9 OFFSET(9) NUMBITS(1) [],
231        ENDPOINT_10 OFFSET(10) NUMBITS(1) [],
232        ENDPOINT_11 OFFSET(11) NUMBITS(1) [],
233    ],
234    pub(crate) IN_STALL [
235        ENDPOINT_0 OFFSET(0) NUMBITS(1) [],
236        ENDPOINT_1 OFFSET(1) NUMBITS(1) [],
237        ENDPOINT_2 OFFSET(2) NUMBITS(1) [],
238        ENDPOINT_3 OFFSET(3) NUMBITS(1) [],
239        ENDPOINT_4 OFFSET(4) NUMBITS(1) [],
240        ENDPOINT_5 OFFSET(5) NUMBITS(1) [],
241        ENDPOINT_6 OFFSET(6) NUMBITS(1) [],
242        ENDPOINT_7 OFFSET(7) NUMBITS(1) [],
243        ENDPOINT_8 OFFSET(8) NUMBITS(1) [],
244        ENDPOINT_9 OFFSET(9) NUMBITS(1) [],
245        ENDPOINT_10 OFFSET(10) NUMBITS(1) [],
246        ENDPOINT_11 OFFSET(11) NUMBITS(1) [],
247    ],
248    pub(crate) CONFIGIN [
249        BUFFER_0 OFFSET(0) NUMBITS(5) [],
250        SIZE_0 OFFSET(8) NUMBITS(7) [],
251        PEND_0 OFFSET(30) NUMBITS(1) [],
252        RDY_0 OFFSET(31) NUMBITS(1) [],
253    ],
254    pub(crate) OUT_ISO [
255        ISO_0 OFFSET(0) NUMBITS(1) [],
256        ISO_1 OFFSET(1) NUMBITS(1) [],
257        ISO_2 OFFSET(2) NUMBITS(1) [],
258        ISO_3 OFFSET(3) NUMBITS(1) [],
259        ISO_4 OFFSET(4) NUMBITS(1) [],
260        ISO_5 OFFSET(5) NUMBITS(1) [],
261        ISO_6 OFFSET(6) NUMBITS(1) [],
262        ISO_7 OFFSET(7) NUMBITS(1) [],
263        ISO_8 OFFSET(8) NUMBITS(1) [],
264        ISO_9 OFFSET(9) NUMBITS(1) [],
265        ISO_10 OFFSET(10) NUMBITS(1) [],
266        ISO_11 OFFSET(11) NUMBITS(1) [],
267    ],
268    pub(crate) IN_ISO [
269        ISO_0 OFFSET(0) NUMBITS(1) [],
270        ISO_1 OFFSET(1) NUMBITS(1) [],
271        ISO_2 OFFSET(2) NUMBITS(1) [],
272        ISO_3 OFFSET(3) NUMBITS(1) [],
273        ISO_4 OFFSET(4) NUMBITS(1) [],
274        ISO_5 OFFSET(5) NUMBITS(1) [],
275        ISO_6 OFFSET(6) NUMBITS(1) [],
276        ISO_7 OFFSET(7) NUMBITS(1) [],
277        ISO_8 OFFSET(8) NUMBITS(1) [],
278        ISO_9 OFFSET(9) NUMBITS(1) [],
279        ISO_10 OFFSET(10) NUMBITS(1) [],
280        ISO_11 OFFSET(11) NUMBITS(1) [],
281    ],
282    pub(crate) DATA_TOGGLE_CLEAR [
283        CLEAR_0 OFFSET(0) NUMBITS(1) [],
284        CLEAR_1 OFFSET(1) NUMBITS(1) [],
285        CLEAR_2 OFFSET(2) NUMBITS(1) [],
286        CLEAR_3 OFFSET(3) NUMBITS(1) [],
287        CLEAR_4 OFFSET(4) NUMBITS(1) [],
288        CLEAR_5 OFFSET(5) NUMBITS(1) [],
289        CLEAR_6 OFFSET(6) NUMBITS(1) [],
290        CLEAR_7 OFFSET(7) NUMBITS(1) [],
291        CLEAR_8 OFFSET(8) NUMBITS(1) [],
292        CLEAR_9 OFFSET(9) NUMBITS(1) [],
293        CLEAR_10 OFFSET(10) NUMBITS(1) [],
294        CLEAR_11 OFFSET(11) NUMBITS(1) [],
295    ],
296    pub(crate) PHY_PINS_SENSE [
297        RX_DP_I OFFSET(0) NUMBITS(1) [],
298        RX_DN_I OFFSET(1) NUMBITS(1) [],
299        RX_D_I OFFSET(2) NUMBITS(1) [],
300        TX_DP_O OFFSET(8) NUMBITS(1) [],
301        TX_DN_O OFFSET(9) NUMBITS(1) [],
302        TX_D_O OFFSET(10) NUMBITS(1) [],
303        TX_SE0_O OFFSET(11) NUMBITS(1) [],
304        TX_OE_O OFFSET(12) NUMBITS(1) [],
305        PWR_SENSE OFFSET(16) NUMBITS(1) [],
306    ],
307    pub(crate) PHY_PINS_DRIVE [
308        DP_O OFFSET(0) NUMBITS(1) [],
309        DN_O OFFSET(1) NUMBITS(1) [],
310        D_O OFFSET(2) NUMBITS(1) [],
311        SE0_O OFFSET(3) NUMBITS(1) [],
312        OE_O OFFSET(4) NUMBITS(1) [],
313        RX_ENABLE_O OFFSET(5) NUMBITS(1) [],
314        DP_PULLUP_EN_O OFFSET(6) NUMBITS(1) [],
315        DN_PULLUP_EN_O OFFSET(7) NUMBITS(1) [],
316        EN OFFSET(16) NUMBITS(1) [],
317    ],
318    pub(crate) PHY_CONFIG [
319        USE_DIFF_RCVR OFFSET(0) NUMBITS(1) [],
320        TX_USE_D_SE0 OFFSET(1) NUMBITS(1) [],
321        EOP_SINGLE_BIT OFFSET(2) NUMBITS(1) [],
322        PINFLIP OFFSET(5) NUMBITS(1) [],
323        USB_REF_DISABLE OFFSET(6) NUMBITS(1) [],
324        TX_OSC_TEST_MODE OFFSET(7) NUMBITS(1) [],
325    ],
326    pub(crate) WAKE_CONTROL [
327        SUSPEND_REQ OFFSET(0) NUMBITS(1) [],
328        WAKE_ACK OFFSET(1) NUMBITS(1) [],
329    ],
330    pub(crate) WAKE_EVENTS [
331        MODULE_ACTIVE OFFSET(0) NUMBITS(1) [],
332        DISCONNECTED OFFSET(8) NUMBITS(1) [],
333        BUS_RESET OFFSET(9) NUMBITS(1) [],
334    ],
335];
336
337// End generated register constants for usbdev
lowrisc/registers/usbdev_regs.rs

lowrisc/registers/
usbdev_regs.rs
