lowrisc/registers/
csrng_regs.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for csrng.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/csrng/data/csrng.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const CSRNG_PARAM_NUM_ALERTS: u32 = 2;
16/// Register width
17pub const CSRNG_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub CsrngRegisters {
21        /// Interrupt State Register
22        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
23        /// Interrupt Enable Register
24        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Test Register
26        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
27        /// Alert Test Register
28        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// Register write enable for all control registers
30        (0x0010 => pub(crate) regwen: ReadWrite<u32, REGWEN::Register>),
31        /// Control register
32        (0x0014 => pub(crate) ctrl: ReadWrite<u32, CTRL::Register>),
33        /// Command request register
34        (0x0018 => pub(crate) cmd_req: ReadWrite<u32, CMD_REQ::Register>),
35        /// Application interface command status register
36        (0x001c => pub(crate) sw_cmd_sts: ReadWrite<u32, SW_CMD_STS::Register>),
37        /// Generate bits returned valid register
38        (0x0020 => pub(crate) genbits_vld: ReadWrite<u32, GENBITS_VLD::Register>),
39        /// Generate bits returned register
40        (0x0024 => pub(crate) genbits: ReadWrite<u32, GENBITS::Register>),
41        /// Internal state number register
42        (0x0028 => pub(crate) int_state_num: ReadWrite<u32, INT_STATE_NUM::Register>),
43        /// Internal state read access register
44        (0x002c => pub(crate) int_state_val: ReadWrite<u32, INT_STATE_VAL::Register>),
45        /// Hardware instance exception status register
46        (0x0030 => pub(crate) hw_exc_sts: ReadWrite<u32, HW_EXC_STS::Register>),
47        /// Recoverable alert status register
48        (0x0034 => pub(crate) recov_alert_sts: ReadWrite<u32, RECOV_ALERT_STS::Register>),
49        /// Hardware detection of error conditions status register
50        (0x0038 => pub(crate) err_code: ReadWrite<u32, ERR_CODE::Register>),
51        /// Test error conditions register
52        (0x003c => pub(crate) err_code_test: ReadWrite<u32, ERR_CODE_TEST::Register>),
53        /// Main state machine state debug register
54        (0x0040 => pub(crate) main_sm_state: ReadWrite<u32, MAIN_SM_STATE::Register>),
55        (0x0044 => @END),
56    }
57}
58
59register_bitfields![u32,
60    /// Common Interrupt Offsets
61    pub(crate) INTR [
62        CS_CMD_REQ_DONE OFFSET(0) NUMBITS(1) [],
63        CS_ENTROPY_REQ OFFSET(1) NUMBITS(1) [],
64        CS_HW_INST_EXC OFFSET(2) NUMBITS(1) [],
65        CS_FATAL_ERR OFFSET(3) NUMBITS(1) [],
66    ],
67    pub(crate) ALERT_TEST [
68        RECOV_ALERT OFFSET(0) NUMBITS(1) [],
69        FATAL_ALERT OFFSET(1) NUMBITS(1) [],
70    ],
71    pub(crate) REGWEN [
72        REGWEN OFFSET(0) NUMBITS(1) [],
73    ],
74    pub(crate) CTRL [
75        ENABLE OFFSET(0) NUMBITS(4) [],
76        SW_APP_ENABLE OFFSET(4) NUMBITS(4) [],
77        READ_INT_STATE OFFSET(8) NUMBITS(4) [],
78    ],
79    pub(crate) CMD_REQ [
80        CMD_REQ OFFSET(0) NUMBITS(32) [],
81    ],
82    pub(crate) SW_CMD_STS [
83        CMD_RDY OFFSET(0) NUMBITS(1) [],
84        CMD_STS OFFSET(1) NUMBITS(1) [],
85    ],
86    pub(crate) GENBITS_VLD [
87        GENBITS_VLD OFFSET(0) NUMBITS(1) [],
88        GENBITS_FIPS OFFSET(1) NUMBITS(1) [],
89    ],
90    pub(crate) GENBITS [
91        GENBITS OFFSET(0) NUMBITS(32) [],
92    ],
93    pub(crate) INT_STATE_NUM [
94        INT_STATE_NUM OFFSET(0) NUMBITS(4) [],
95    ],
96    pub(crate) INT_STATE_VAL [
97        INT_STATE_VAL OFFSET(0) NUMBITS(32) [],
98    ],
99    pub(crate) HW_EXC_STS [
100        HW_EXC_STS OFFSET(0) NUMBITS(16) [],
101    ],
102    pub(crate) RECOV_ALERT_STS [
103        ENABLE_FIELD_ALERT OFFSET(0) NUMBITS(1) [],
104        SW_APP_ENABLE_FIELD_ALERT OFFSET(1) NUMBITS(1) [],
105        READ_INT_STATE_FIELD_ALERT OFFSET(2) NUMBITS(1) [],
106        ACMD_FLAG0_FIELD_ALERT OFFSET(3) NUMBITS(1) [],
107        CS_BUS_CMP_ALERT OFFSET(12) NUMBITS(1) [],
108        CS_MAIN_SM_ALERT OFFSET(13) NUMBITS(1) [],
109    ],
110    pub(crate) ERR_CODE [
111        SFIFO_CMD_ERR OFFSET(0) NUMBITS(1) [],
112        SFIFO_GENBITS_ERR OFFSET(1) NUMBITS(1) [],
113        SFIFO_CMDREQ_ERR OFFSET(2) NUMBITS(1) [],
114        SFIFO_RCSTAGE_ERR OFFSET(3) NUMBITS(1) [],
115        SFIFO_KEYVRC_ERR OFFSET(4) NUMBITS(1) [],
116        SFIFO_UPDREQ_ERR OFFSET(5) NUMBITS(1) [],
117        SFIFO_BENCREQ_ERR OFFSET(6) NUMBITS(1) [],
118        SFIFO_BENCACK_ERR OFFSET(7) NUMBITS(1) [],
119        SFIFO_PDATA_ERR OFFSET(8) NUMBITS(1) [],
120        SFIFO_FINAL_ERR OFFSET(9) NUMBITS(1) [],
121        SFIFO_GBENCACK_ERR OFFSET(10) NUMBITS(1) [],
122        SFIFO_GRCSTAGE_ERR OFFSET(11) NUMBITS(1) [],
123        SFIFO_GGENREQ_ERR OFFSET(12) NUMBITS(1) [],
124        SFIFO_GADSTAGE_ERR OFFSET(13) NUMBITS(1) [],
125        SFIFO_GGENBITS_ERR OFFSET(14) NUMBITS(1) [],
126        SFIFO_BLKENC_ERR OFFSET(15) NUMBITS(1) [],
127        CMD_STAGE_SM_ERR OFFSET(20) NUMBITS(1) [],
128        MAIN_SM_ERR OFFSET(21) NUMBITS(1) [],
129        DRBG_GEN_SM_ERR OFFSET(22) NUMBITS(1) [],
130        DRBG_UPDBE_SM_ERR OFFSET(23) NUMBITS(1) [],
131        DRBG_UPDOB_SM_ERR OFFSET(24) NUMBITS(1) [],
132        AES_CIPHER_SM_ERR OFFSET(25) NUMBITS(1) [],
133        CMD_GEN_CNT_ERR OFFSET(26) NUMBITS(1) [],
134        FIFO_WRITE_ERR OFFSET(28) NUMBITS(1) [],
135        FIFO_READ_ERR OFFSET(29) NUMBITS(1) [],
136        FIFO_STATE_ERR OFFSET(30) NUMBITS(1) [],
137    ],
138    pub(crate) ERR_CODE_TEST [
139        ERR_CODE_TEST OFFSET(0) NUMBITS(5) [],
140    ],
141    pub(crate) MAIN_SM_STATE [
142        MAIN_SM_STATE OFFSET(0) NUMBITS(8) [],
143    ],
144];
145
146// End generated register constants for csrng
lowrisc/registers/csrng_regs.rs

lowrisc/registers/
csrng_regs.rs
