earlgrey/registers/
sensor_ctrl_regs.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for sensor_ctrl.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alert events from ast
15pub const SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS: u32 = 11;
16/// Number of local events
17pub const SENSOR_CTRL_PARAM_NUM_LOCAL_EVENTS: u32 = 1;
18/// Number of alerts sent from sensor control
19pub const SENSOR_CTRL_PARAM_NUM_ALERTS: u32 = 2;
20/// Number of IO rails
21pub const SENSOR_CTRL_PARAM_NUM_IO_RAILS: u32 = 2;
22/// Register width
23pub const SENSOR_CTRL_PARAM_REG_WIDTH: u32 = 32;
24
25register_structs! {
26    pub SensorCtrlRegisters {
27        /// Interrupt State Register
28        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
29        /// Interrupt Enable Register
30        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
31        /// Interrupt Test Register
32        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
33        /// Alert Test Register
34        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
35        /// Controls the configurability of !!FATAL_ALERT_EN register.
36        (0x0010 => pub(crate) cfg_regwen: ReadWrite<u32, CFG_REGWEN::Register>),
37        /// Alert trigger test
38        (0x0014 => pub(crate) alert_trig: [ReadWrite<u32, ALERT_TRIG::Register>; 1]),
39        /// Each bit marks a corresponding alert as fatal or recoverable.
40        (0x0018 => pub(crate) fatal_alert_en: [ReadWrite<u32, FATAL_ALERT_EN::Register>; 1]),
41        /// Each bit represents a recoverable alert that has been triggered by AST.
42        (0x001c => pub(crate) recov_alert: [ReadWrite<u32, RECOV_ALERT::Register>; 1]),
43        /// Each bit represents a fatal alert that has been triggered by AST.
44        (0x0020 => pub(crate) fatal_alert: [ReadWrite<u32, FATAL_ALERT::Register>; 1]),
45        /// Status readback for ast
46        (0x0024 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
47        (0x0028 => @END),
48    }
49}
50
51register_bitfields![u32,
52    /// Common Interrupt Offsets
53    pub(crate) INTR [
54        IO_STATUS_CHANGE OFFSET(0) NUMBITS(1) [],
55        INIT_STATUS_CHANGE OFFSET(1) NUMBITS(1) [],
56    ],
57    pub(crate) ALERT_TEST [
58        RECOV_ALERT OFFSET(0) NUMBITS(1) [],
59        FATAL_ALERT OFFSET(1) NUMBITS(1) [],
60    ],
61    pub(crate) CFG_REGWEN [
62        EN OFFSET(0) NUMBITS(1) [],
63    ],
64    pub(crate) ALERT_TRIG [
65        VAL_0 OFFSET(0) NUMBITS(1) [],
66        VAL_1 OFFSET(1) NUMBITS(1) [],
67        VAL_2 OFFSET(2) NUMBITS(1) [],
68        VAL_3 OFFSET(3) NUMBITS(1) [],
69        VAL_4 OFFSET(4) NUMBITS(1) [],
70        VAL_5 OFFSET(5) NUMBITS(1) [],
71        VAL_6 OFFSET(6) NUMBITS(1) [],
72        VAL_7 OFFSET(7) NUMBITS(1) [],
73        VAL_8 OFFSET(8) NUMBITS(1) [],
74        VAL_9 OFFSET(9) NUMBITS(1) [],
75        VAL_10 OFFSET(10) NUMBITS(1) [],
76    ],
77    pub(crate) FATAL_ALERT_EN [
78        VAL_0 OFFSET(0) NUMBITS(1) [],
79        VAL_1 OFFSET(1) NUMBITS(1) [],
80        VAL_2 OFFSET(2) NUMBITS(1) [],
81        VAL_3 OFFSET(3) NUMBITS(1) [],
82        VAL_4 OFFSET(4) NUMBITS(1) [],
83        VAL_5 OFFSET(5) NUMBITS(1) [],
84        VAL_6 OFFSET(6) NUMBITS(1) [],
85        VAL_7 OFFSET(7) NUMBITS(1) [],
86        VAL_8 OFFSET(8) NUMBITS(1) [],
87        VAL_9 OFFSET(9) NUMBITS(1) [],
88        VAL_10 OFFSET(10) NUMBITS(1) [],
89    ],
90    pub(crate) RECOV_ALERT [
91        VAL_0 OFFSET(0) NUMBITS(1) [],
92        VAL_1 OFFSET(1) NUMBITS(1) [],
93        VAL_2 OFFSET(2) NUMBITS(1) [],
94        VAL_3 OFFSET(3) NUMBITS(1) [],
95        VAL_4 OFFSET(4) NUMBITS(1) [],
96        VAL_5 OFFSET(5) NUMBITS(1) [],
97        VAL_6 OFFSET(6) NUMBITS(1) [],
98        VAL_7 OFFSET(7) NUMBITS(1) [],
99        VAL_8 OFFSET(8) NUMBITS(1) [],
100        VAL_9 OFFSET(9) NUMBITS(1) [],
101        VAL_10 OFFSET(10) NUMBITS(1) [],
102    ],
103    pub(crate) FATAL_ALERT [
104        VAL_0 OFFSET(0) NUMBITS(1) [],
105        VAL_1 OFFSET(1) NUMBITS(1) [],
106        VAL_2 OFFSET(2) NUMBITS(1) [],
107        VAL_3 OFFSET(3) NUMBITS(1) [],
108        VAL_4 OFFSET(4) NUMBITS(1) [],
109        VAL_5 OFFSET(5) NUMBITS(1) [],
110        VAL_6 OFFSET(6) NUMBITS(1) [],
111        VAL_7 OFFSET(7) NUMBITS(1) [],
112        VAL_8 OFFSET(8) NUMBITS(1) [],
113        VAL_9 OFFSET(9) NUMBITS(1) [],
114        VAL_10 OFFSET(10) NUMBITS(1) [],
115        VAL_11 OFFSET(11) NUMBITS(1) [],
116    ],
117    pub(crate) STATUS [
118        AST_INIT_DONE OFFSET(0) NUMBITS(1) [],
119        IO_POK OFFSET(1) NUMBITS(2) [],
120    ],
121];
122
123// End generated register constants for sensor_ctrl
earlgrey/registers/sensor_ctrl_regs.rs

earlgrey/registers/
sensor_ctrl_regs.rs
