earlgrey/
chip_config.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Chip specific configuration.
6//!
7//! This file includes a common configuration trait and pre-defined constants
8//! values for different implementations and uses of the same earlgrey chip. For
9//! example, running the chip on an FPGA requires different parameters from
10//! running it in a verilog simulator.  Additionally, chips on different
11//! platforms can be used differently, so this also permits changing values like
12//! the UART baud rate to enable better debugging on platforms that can support
13//! it.
14
15/// Earlgrey configuration based on the target device.
16pub trait EarlGreyConfig {
17    /// Identifier for the platform. This is useful for debugging to confirm the
18    /// correct configuration of the chip is being used.
19    const NAME: &'static str;
20
21    /// The clock speed of the CPU in Hz.
22    const CPU_FREQ: u32;
23
24    /// The clock speed of the peripherals in Hz.
25    const PERIPHERAL_FREQ: u32;
26
27    /// The clock of the AON Timer
28    const AON_TIMER_FREQ: u32;
29
30    /// The baud rate for UART. This allows for a version of the chip that can
31    /// support a faster baud rate to use it to help with debugging.
32    const UART_BAUDRATE: u32;
33}