sifive/
rtc.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Real Time Clock (RTC) driver.
6
7use kernel::utilities::registers::interfaces::Writeable;
8use kernel::utilities::registers::{register_bitfields, ReadWrite};
9use kernel::utilities::StaticRef;
10
11#[repr(C)]
12pub struct RtcRegisters {
13    /// RTC Configuration Register
14    rtccfg: ReadWrite<u32, rtccfg::Register>,
15    _reserved1: [u8; 4],
16    /// RTC Counter Low Register
17    rtclo: ReadWrite<u32, rtclo::Register>,
18    /// RTC Counter High Register
19    rtchi: ReadWrite<u32>,
20    /// RTC Scaled Counter Register
21    rtcs: ReadWrite<u32>,
22    _reserved2: [u8; 12],
23    /// RTC Compare Register
24    rtccmp: ReadWrite<u32, rtccmp::Register>,
25}
26
27register_bitfields![u32,
28    rtccfg [
29        cmpip OFFSET(28) NUMBITS(1) [],
30        enalways OFFSET(12) NUMBITS(1) [],
31        scale OFFSET(0) NUMBITS(4) []
32    ],
33    rtclo [
34        rtclo OFFSET(0) NUMBITS(32) []
35    ],
36    rtchi [
37        rtchi OFFSET(0) NUMBITS(16) []
38    ],
39    rtccmp [
40        rtccmp OFFSET(0) NUMBITS(32) []
41    ]
42];
43
44pub struct Rtc {
45    registers: StaticRef<RtcRegisters>,
46}
47
48impl Rtc {
49    pub const fn new(base: StaticRef<RtcRegisters>) -> Rtc {
50        Rtc { registers: base }
51    }
52
53    /// Disable the RTC so it does not generate interrupts.
54    pub fn disable(&self) {
55        let regs = self.registers;
56
57        // Turn the interrupt compare off so we don't get any RTC interrupts.
58        regs.rtccfg.write(rtccfg::enalways::CLEAR);
59
60        // Set the compare time to as large as possible
61        regs.rtccmp.set(0xFFFF_FFFF);
62    }
63}
sifive/rtc.rs

sifive/
rtc.rs
