sifive/
rtc.rs

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
// Licensed under the Apache License, Version 2.0 or the MIT License.
// SPDX-License-Identifier: Apache-2.0 OR MIT
// Copyright Tock Contributors 2022.

//! Real Time Clock (RTC) driver.

use kernel::utilities::registers::interfaces::Writeable;
use kernel::utilities::registers::{register_bitfields, ReadWrite};
use kernel::utilities::StaticRef;

#[repr(C)]
pub struct RtcRegisters {
    /// RTC Configuration Register
    rtccfg: ReadWrite<u32, rtccfg::Register>,
    _reserved1: [u8; 4],
    /// RTC Counter Low Register
    rtclo: ReadWrite<u32, rtclo::Register>,
    /// RTC Counter High Register
    rtchi: ReadWrite<u32>,
    /// RTC Scaled Counter Register
    rtcs: ReadWrite<u32>,
    _reserved2: [u8; 12],
    /// RTC Compare Register
    rtccmp: ReadWrite<u32, rtccmp::Register>,
}

register_bitfields![u32,
    rtccfg [
        cmpip OFFSET(28) NUMBITS(1) [],
        enalways OFFSET(12) NUMBITS(1) [],
        scale OFFSET(0) NUMBITS(4) []
    ],
    rtclo [
        rtclo OFFSET(0) NUMBITS(32) []
    ],
    rtchi [
        rtchi OFFSET(0) NUMBITS(16) []
    ],
    rtccmp [
        rtccmp OFFSET(0) NUMBITS(32) []
    ]
];

pub struct Rtc {
    registers: StaticRef<RtcRegisters>,
}

impl Rtc {
    pub const fn new(base: StaticRef<RtcRegisters>) -> Rtc {
        Rtc { registers: base }
    }

    /// Disable the RTC so it does not generate interrupts.
    pub fn disable(&self) {
        let regs = self.registers;

        // Turn the interrupt compare off so we don't get any RTC interrupts.
        regs.rtccfg.write(rtccfg::enalways::CLEAR);

        // Set the compare time to as large as possible
        regs.rtccmp.set(0xFFFF_FFFF);
    }
}