psoc62xa/
chip.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright OxidOS Automotive 2025 SRL.
4
5use kernel::platform::chip::Chip;
6use kernel::platform::chip::InterruptService;
7
8use crate::{cpuss, gpio, hsiom, peri, scb, srss, tcpwm};
9use cortexm0p::{CortexM0P, CortexMVariant};
10
11pub struct Psoc62xa<'a, I: InterruptService + 'a> {
12    mpu: cortexm0p::mpu::MPU,
13    userspace_kernel_boundary: cortexm0p::syscall::SysCall,
14    interrupt_service: &'a I,
15}
16
17impl<'a, I: InterruptService> Psoc62xa<'a, I> {
18    pub fn new(interrupt_service: &'a I) -> Self {
19        Self {
20            mpu: unsafe { cortexm0p::mpu::new() },
21            userspace_kernel_boundary: unsafe { cortexm0p::syscall::SysCall::new() },
22            interrupt_service,
23        }
24    }
25}
26
27impl<I: InterruptService> Chip for Psoc62xa<'_, I> {
28    type MPU = cortexm0p::mpu::MPU;
29    type UserspaceKernelBoundary = cortexm0p::syscall::SysCall;
30
31    fn mpu(&self) -> &Self::MPU {
32        &self.mpu
33    }
34
35    fn sleep(&self) {
36        unsafe {
37            cortexm0p::support::wfi();
38        }
39    }
40
41    unsafe fn atomic<F, R>(&self, f: F) -> R
42    where
43        F: FnOnce() -> R,
44    {
45        cortexm0p::support::atomic(f)
46    }
47
48    unsafe fn print_state(&self, writer: &mut dyn core::fmt::Write) {
49        CortexM0P::print_cortexm_state(writer);
50    }
51
52    fn userspace_kernel_boundary(&self) -> &Self::UserspaceKernelBoundary {
53        &self.userspace_kernel_boundary
54    }
55
56    fn has_pending_interrupts(&self) -> bool {
57        unsafe { cortexm0p::nvic::has_pending() }
58    }
59
60    fn service_pending_interrupts(&self) {
61        unsafe {
62            while let Some(interrupt) = cortexm0p::nvic::next_pending() {
63                if !self.interrupt_service.service_interrupt(interrupt) {
64                    panic!("unhandled interrupt {}", interrupt);
65                }
66                let n = cortexm0p::nvic::Nvic::new(interrupt);
67                n.clear_pending();
68                n.enable();
69            }
70            while let Some(interrupt) = cortexm0p::nvic::next_pending() {
71                let nvic = cortexm0p::nvic::Nvic::new(interrupt);
72                nvic.clear_pending();
73                nvic.enable();
74            }
75        }
76    }
77}
78
79pub struct PsoC62xaDefaultPeripherals<'a> {
80    pub cpuss: cpuss::Cpuss,
81    pub gpio: gpio::PsocPins<'a>,
82    pub hsiom: hsiom::Hsiom,
83    pub peri: peri::Peri,
84    pub scb: scb::Scb<'a>,
85    pub srss: srss::Srss,
86    pub tcpwm: tcpwm::Tcpwm0<'a>,
87}
88
89impl PsoC62xaDefaultPeripherals<'_> {
90    pub fn new() -> Self {
91        Self {
92            cpuss: cpuss::Cpuss::new(),
93            gpio: gpio::PsocPins::new(),
94            hsiom: hsiom::Hsiom::new(),
95            peri: peri::Peri::new(),
96            scb: scb::Scb::new(),
97            srss: srss::Srss::new(),
98            tcpwm: tcpwm::Tcpwm0::new(),
99        }
100    }
101}
102
103impl InterruptService for PsoC62xaDefaultPeripherals<'_> {
104    unsafe fn service_interrupt(&self, interrupt: u32) -> bool {
105        match interrupt {
106            0 => {
107                self.scb.handle_interrupt();
108                self.tcpwm.handle_interrupt();
109            }
110            1 => {
111                // We use interrupt number 1 for GPIO so we don't
112                // check for all of the GPIO ports on every non-GPIO
113                // releated interrupt.
114                self.gpio.handle_interrupt();
115            }
116            _ => return false,
117        }
118        true
119    }
120}
psoc62xa/chip.rs

psoc62xa/
chip.rs
