1use kernel::utilities::registers::register_bitfields;
6
7#[cfg(any(
9 target_arch = "riscv32",
10 all(not(target_arch = "riscv32"), not(target_arch = "riscv64"))
11))]
12register_bitfields![usize,
13 pub pmpcfg [
14 r0 OFFSET(0) NUMBITS(1) [],
15 w0 OFFSET(1) NUMBITS(1) [],
16 x0 OFFSET(2) NUMBITS(1) [],
17 a0 OFFSET(3) NUMBITS(2) [
18 OFF = 0,
19 TOR = 1,
20 NA4 = 2,
21 NAPOT = 3
22 ],
23 l0 OFFSET(7) NUMBITS(1) [],
24
25 r1 OFFSET(8) NUMBITS(1) [],
26 w1 OFFSET(9) NUMBITS(1) [],
27 x1 OFFSET(10) NUMBITS(1) [],
28 a1 OFFSET(11) NUMBITS(2) [
29 OFF = 0,
30 TOR = 1,
31 NA4 = 2,
32 NAPOT = 3
33 ],
34 l1 OFFSET(15) NUMBITS(1) [],
35
36 r2 OFFSET(16) NUMBITS(1) [],
37 w2 OFFSET(17) NUMBITS(1) [],
38 x2 OFFSET(18) NUMBITS(1) [],
39 a2 OFFSET(19) NUMBITS(2) [
40 OFF = 0,
41 TOR = 1,
42 NA4 = 2,
43 NAPOT = 3
44 ],
45 l2 OFFSET(23) NUMBITS(1) [],
46
47 r3 OFFSET(24) NUMBITS(1) [],
48 w3 OFFSET(25) NUMBITS(1) [],
49 x3 OFFSET(26) NUMBITS(1) [],
50 a3 OFFSET(27) NUMBITS(2) [
51 OFF = 0,
52 TOR = 1,
53 NA4 = 2,
54 NAPOT = 3
55 ],
56 l3 OFFSET(31) NUMBITS(1) []
57 ]
58];
59
60#[cfg(target_arch = "riscv64")]
61register_bitfields![usize,
62 pub pmpcfg [
63 r0 OFFSET(0) NUMBITS(1) [],
64 w0 OFFSET(1) NUMBITS(1) [],
65 x0 OFFSET(2) NUMBITS(1) [],
66 a0 OFFSET(3) NUMBITS(2) [
67 OFF = 0,
68 TOR = 1,
69 NA4 = 2,
70 NAPOT = 3
71 ],
72 l0 OFFSET(7) NUMBITS(1) [],
73
74 r1 OFFSET(8) NUMBITS(1) [],
75 w1 OFFSET(9) NUMBITS(1) [],
76 x1 OFFSET(10) NUMBITS(1) [],
77 a1 OFFSET(11) NUMBITS(2) [
78 OFF = 0,
79 TOR = 1,
80 NA4 = 2,
81 NAPOT = 3
82 ],
83 l1 OFFSET(15) NUMBITS(1) [],
84
85 r2 OFFSET(16) NUMBITS(1) [],
86 w2 OFFSET(17) NUMBITS(1) [],
87 x2 OFFSET(18) NUMBITS(1) [],
88 a2 OFFSET(19) NUMBITS(2) [
89 OFF = 0,
90 TOR = 1,
91 NA4 = 2,
92 NAPOT = 3
93 ],
94 l2 OFFSET(23) NUMBITS(1) [],
95
96 r3 OFFSET(24) NUMBITS(1) [],
97 w3 OFFSET(25) NUMBITS(1) [],
98 x3 OFFSET(26) NUMBITS(1) [],
99 a3 OFFSET(27) NUMBITS(2) [
100 OFF = 0,
101 TOR = 1,
102 NA4 = 2,
103 NAPOT = 3
104 ],
105 l3 OFFSET(31) NUMBITS(1) [],
106
107 r4 OFFSET(32) NUMBITS(1) [],
108 w4 OFFSET(33) NUMBITS(1) [],
109 x4 OFFSET(34) NUMBITS(1) [],
110 a4 OFFSET(35) NUMBITS(2) [
111 OFF = 0,
112 TOR = 1,
113 NA4 = 2,
114 NAPOT = 3
115 ],
116 l4 OFFSET(39) NUMBITS(1) [],
117
118 r5 OFFSET(40) NUMBITS(1) [],
119 w5 OFFSET(41) NUMBITS(1) [],
120 x5 OFFSET(42) NUMBITS(1) [],
121 a5 OFFSET(43) NUMBITS(2) [
122 OFF = 0,
123 TOR = 1,
124 NA4 = 2,
125 NAPOT = 3
126 ],
127 l5 OFFSET(47) NUMBITS(1) [],
128
129 r6 OFFSET(48) NUMBITS(1) [],
130 w6 OFFSET(49) NUMBITS(1) [],
131 x6 OFFSET(50) NUMBITS(1) [],
132 a6 OFFSET(51) NUMBITS(2) [
133 OFF = 0,
134 TOR = 1,
135 NA4 = 2,
136 NAPOT = 3
137 ],
138 l6 OFFSET(55) NUMBITS(1) [],
139
140 r7 OFFSET(56) NUMBITS(1) [],
141 w7 OFFSET(57) NUMBITS(1) [],
142 x7 OFFSET(58) NUMBITS(1) [],
143 a7 OFFSET(59) NUMBITS(2) [
144 OFF = 0,
145 TOR = 1,
146 NA4 = 2,
147 NAPOT = 3
148 ],
149 l7 OFFSET(63) NUMBITS(1) []
150 ]
151];