imxrt10xx/ccm_analog.rs
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! CCM Analog peripheral
6
7// Generated following
8//
9// 1. Use svd2regs.py to import the memory layout and all fields
10// 2. For each reg, set, clear, toggle, grouping, replace it with
11// a Groups struct.
12// 3. Remove unused
13
14use kernel::utilities::registers::interfaces::{Readable, Writeable};
15use kernel::utilities::registers::{
16 register_bitfields, register_structs, ReadWrite, RegisterLongName, WriteOnly,
17};
18use kernel::utilities::StaticRef;
19
20/// Many CCM_ANALOG registers are laid out with additional set, clear, and toggle
21/// registers. This groups them together into an extended register.
22///
23/// Selecting suffix 'SCT' given the mention in the reference manual:
24///
25/// > A set of SCT registeres is offered for registers in many modules [...]
26///
27/// Although the CCM_ANALOG memory map indicates the SCT registers are R/W,
28/// the reference manual front-matter (section 1.5.2) indicates that they should
29/// be treated as as write only:
30///
31/// > The SCT registers always read back 0, and should be considered write-only.
32#[repr(C)]
33struct RegisterSCT<R: RegisterLongName = ()> {
34 /// The normal register
35 reg: ReadWrite<u32, R>,
36 /// Write 1 sets bits in reg
37 set: WriteOnly<u32, R>,
38 /// Write 1 clears bits in reg
39 clear: WriteOnly<u32, R>,
40 /// Write 1 toggles bits in reg
41 toggle: WriteOnly<u32, R>,
42}
43
44register_structs! {
45 /// CCM_ANALOG
46 CcmAnalogRegisters {
47 /// Analog ARM PLL control Register
48 (0x000 => pll_arm: RegisterSCT<PLL_ARM::Register>),
49 /// Analog USB1 480MHz PLL Control Register
50 (0x010 => pll_usb1: RegisterSCT<PLL_USB1::Register>),
51 /// Analog USB2 480MHz PLL Control Register
52 (0x020 => pll_usb2: RegisterSCT<PLL_USB2::Register>),
53 /// Analog System PLL Control Register
54 (0x030 => pll_sys: RegisterSCT<PLL_SYS::Register>),
55 /// 528MHz System PLL Spread Spectrum Register
56 (0x040 => pll_sys_ss: ReadWrite<u32, PLL_SYS_SS::Register>),
57 (0x044 => _reserved0),
58 /// Numerator of 528MHz System PLL Fractional Loop Divider Register
59 (0x050 => pll_sys_num: ReadWrite<u32>),
60 (0x054 => _reserved1),
61 /// Denominator of 528MHz System PLL Fractional Loop Divider Register
62 (0x060 => pll_sys_denom: ReadWrite<u32>),
63 (0x064 => _reserved2),
64 /// Analog Audio PLL control Register
65 (0x070 => pll_audio: RegisterSCT<PLL_AUDIO::Register>),
66 /// Numerator of Audio PLL Fractional Loop Divider Register
67 (0x080 => pll_audio_num: ReadWrite<u32>),
68 (0x084 => _reserved3),
69 /// Denominator of Audio PLL Fractional Loop Divider Register
70 (0x090 => pll_audio_denom: ReadWrite<u32>),
71 (0x094 => _reserved4),
72 /// Analog Video PLL control Register
73 (0x0A0 => pll_video: RegisterSCT<PLL_VIDEO::Register>),
74 /// Numerator of Video PLL Fractional Loop Divider Register
75 (0x0B0 => pll_video_num: ReadWrite<u32>),
76 (0x0B4 => _reserved5),
77 /// Denominator of Video PLL Fractional Loop Divider Register
78 (0x0C0 => pll_video_denom: ReadWrite<u32>),
79 (0x0C4 => _reserved6),
80 /// Analog ENET PLL Control Register
81 (0x0E0 => pll_enet: RegisterSCT<PLL_ENET::Register>),
82 /// 480MHz Clock (PLL3) Phase Fractional Divider Control Register
83 (0x0F0 => pfd_480: RegisterSCT<PFD_480::Register>),
84 /// 528MHz Clock (PLL2) Phase Fractional Divider Control Register
85 (0x100 => pfd_528: RegisterSCT<PFD_528::Register>),
86 (0x110 => _reserved7),
87 /// Miscellaneous Register 0
88 (0x150 => misc0: RegisterSCT<MISC0::Register>),
89 /// Miscellaneous Register 1
90 (0x160 => misc1: RegisterSCT<MISC1::Register>),
91 /// Miscellaneous Register 2
92 (0x170 => misc2: RegisterSCT<MISC2::Register>),
93 (0x180 => @END),
94 }
95}
96
97register_bitfields![u32,
98 PLL_ARM [
99 /// This field controls the PLL loop divider
100 DIV_SELECT OFFSET(0) NUMBITS(7) [],
101 /// Powers down the PLL.
102 POWERDOWN OFFSET(12) NUMBITS(1) [],
103 /// Enable the clock output.
104 ENABLE OFFSET(13) NUMBITS(1) [],
105 /// Determines the bypass source
106 BYPASS_CLK_SRC OFFSET(14) NUMBITS(2) [
107 /// Select the 24MHz oscillator as source.
108 SelectThe24MHzOscillatorAsSource = 0,
109 /// Select the CLK1_N / CLK1_P as source.
110 SelectTheCLK1_NCLK1_PAsSource = 1
111 ],
112 /// Bypass the PLL.
113 BYPASS OFFSET(16) NUMBITS(1) [],
114 /// Reserved
115 PLL_SEL OFFSET(19) NUMBITS(1) [],
116 /// 1 - PLL is currently locked. 0 - PLL is not currently locked.
117 LOCK OFFSET(31) NUMBITS(1) []
118 ],
119 PLL_USB1 [
120 /// This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.
121 DIV_SELECT OFFSET(1) NUMBITS(1) [],
122 /// Powers the 9-phase PLL outputs for USBPHYn
123 EN_USB_CLKS OFFSET(6) NUMBITS(1) [
124 /// PLL outputs for USBPHYn off.
125 PLLOutputsForUSBPHYnOff = 0,
126 /// PLL outputs for USBPHYn on.
127 PLLOutputsForUSBPHYnOn = 1
128 ],
129 /// Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup
130 POWER OFFSET(12) NUMBITS(1) [],
131 /// Enable the PLL clock output.
132 ENABLE OFFSET(13) NUMBITS(1) [],
133 /// Determines the bypass source.
134 BYPASS_CLK_SRC OFFSET(14) NUMBITS(2) [
135 /// Select the 24MHz oscillator as source.
136 SelectThe24MHzOscillatorAsSource = 0,
137 /// Select the CLK1_N / CLK1_P as source.
138 SelectTheCLK1_NCLK1_PAsSource = 1
139 ],
140 /// Bypass the PLL.
141 BYPASS OFFSET(16) NUMBITS(1) [],
142 /// 1 - PLL is currently locked. 0 - PLL is not currently locked.
143 LOCK OFFSET(31) NUMBITS(1) []
144 ],
145 PLL_USB2 [
146 /// This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.
147 DIV_SELECT OFFSET(1) NUMBITS(1) [],
148 /// 0: 8-phase PLL outputs for USBPHY1 are powered down
149 EN_USB_CLKS OFFSET(6) NUMBITS(1) [],
150 /// Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup
151 POWER OFFSET(12) NUMBITS(1) [],
152 /// Enable the PLL clock output.
153 ENABLE OFFSET(13) NUMBITS(1) [],
154 /// Determines the bypass source.
155 BYPASS_CLK_SRC OFFSET(14) NUMBITS(2) [
156 /// Select the 24MHz oscillator as source.
157 SelectThe24MHzOscillatorAsSource = 0,
158 /// Select the CLK1_N / CLK1_P as source.
159 SelectTheCLK1_NCLK1_PAsSource = 1
160 ],
161 /// Bypass the PLL.
162 BYPASS OFFSET(16) NUMBITS(1) [],
163 /// 1 - PLL is currently locked. 0 - PLL is not currently locked.
164 LOCK OFFSET(31) NUMBITS(1) []
165 ],
166 PLL_SYS [
167 /// This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.
168 DIV_SELECT OFFSET(0) NUMBITS(1) [],
169 /// Powers down the PLL.
170 POWERDOWN OFFSET(12) NUMBITS(1) [],
171 /// Enable PLL output
172 ENABLE OFFSET(13) NUMBITS(1) [],
173 /// Determines the bypass source.
174 BYPASS_CLK_SRC OFFSET(14) NUMBITS(2) [
175 /// Select the 24MHz oscillator as source.
176 SelectThe24MHzOscillatorAsSource = 0,
177 /// Select the CLK1_N / CLK1_P as source.
178 SelectTheCLK1_NCLK1_PAsSource = 1
179 ],
180 /// Bypass the PLL.
181 BYPASS OFFSET(16) NUMBITS(1) [],
182 /// 1 - PLL is currently locked; 0 - PLL is not currently locked.
183 LOCK OFFSET(31) NUMBITS(1) []
184 ],
185 PLL_AUDIO [
186 /// This field controls the PLL loop divider. Valid range for DIV_SELECT divider val
187 DIV_SELECT OFFSET(0) NUMBITS(7) [],
188 /// Powers down the PLL.
189 POWERDOWN OFFSET(12) NUMBITS(1) [],
190 /// Enable PLL output
191 ENABLE OFFSET(13) NUMBITS(1) [],
192 /// Determines the bypass source.
193 BYPASS_CLK_SRC OFFSET(14) NUMBITS(2) [
194 /// Select the 24MHz oscillator as source.
195 SelectThe24MHzOscillatorAsSource = 0,
196 /// Select the CLK1_N / CLK1_P as source.
197 SelectTheCLK1_NCLK1_PAsSource = 1
198 ],
199 /// Bypass the PLL.
200 BYPASS OFFSET(16) NUMBITS(1) [],
201 /// These bits implement a divider after the PLL, but before the enable and bypass m
202 POST_DIV_SELECT OFFSET(19) NUMBITS(2) [
203 /// Divide by 4.
204 DivideBy4 = 0,
205 /// Divide by 2.
206 DivideBy2 = 1,
207 /// Divide by 1.
208 DivideBy1 = 2
209 ],
210 /// 1 - PLL is currently locked. 0 - PLL is not currently locked.
211 LOCK OFFSET(31) NUMBITS(1) []
212 ],
213 PLL_SYS_SS [
214 /// Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.
215 STEP OFFSET(0) NUMBITS(15) [],
216 /// Enable bit
217 ENABLE OFFSET(15) NUMBITS(1) [
218 /// Spread spectrum modulation disabled
219 SpreadSpectrumModulationDisabled = 0,
220 /// Soread spectrum modulation enabled
221 SoreadSpectrumModulationEnabled = 1
222 ],
223 /// Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.
224 STOP OFFSET(16) NUMBITS(16) []
225 ],
226 PLL_VIDEO [
227 /// This field controls the PLL loop divider. Valid range for DIV_SELECT divider val
228 DIV_SELECT OFFSET(0) NUMBITS(7) [],
229 /// Powers down the PLL.
230 POWERDOWN OFFSET(12) NUMBITS(1) [],
231 /// Enalbe PLL output
232 ENABLE OFFSET(13) NUMBITS(1) [],
233 /// Determines the bypass source.
234 BYPASS_CLK_SRC OFFSET(14) NUMBITS(2) [
235 /// Select the 24MHz oscillator as source.
236 SelectThe24MHzOscillatorAsSource = 0,
237 /// Select the CLK1_N / CLK1_P as source.
238 SelectTheCLK1_NCLK1_PAsSource = 1
239 ],
240 /// Bypass the PLL.
241 BYPASS OFFSET(16) NUMBITS(1) [],
242 /// These bits implement a divider after the PLL, but before the enable and bypass m
243 POST_DIV_SELECT OFFSET(19) NUMBITS(2) [
244 /// Divide by 4.
245 DivideBy4 = 0,
246 /// Divide by 2.
247 DivideBy2 = 1,
248 /// Divide by 1.
249 DivideBy1 = 2
250 ],
251 /// 1 - PLL is currently locked; 0 - PLL is not currently locked.
252 LOCK OFFSET(31) NUMBITS(1) []
253 ],
254 PLL_ENET [
255 /// Controls the frequency of the ethernet reference clock
256 DIV_SELECT OFFSET(0) NUMBITS(2) [],
257 /// Controls the frequency of the ENET2 reference clock.
258 ENET2_DIV_SELECT OFFSET(2) NUMBITS(2) [
259 /// 25MHz
260 _25MHz = 0,
261 /// 50MHz
262 _50MHz = 1,
263 /// 100MHz (not 50% duty cycle)
264 _100MHzNot50DutyCycle = 2,
265 /// 125MHz
266 _125MHz = 3
267 ],
268 /// Powers down the PLL.
269 POWERDOWN OFFSET(12) NUMBITS(1) [],
270 /// Enable the PLL providing the ENET reference clock.
271 ENABLE OFFSET(13) NUMBITS(1) [],
272 /// Determines the bypass source.
273 BYPASS_CLK_SRC OFFSET(14) NUMBITS(2) [
274 /// Select the 24MHz oscillator as source.
275 SelectThe24MHzOscillatorAsSource = 0,
276 /// Select the CLK1_N / CLK1_P as source.
277 SelectTheCLK1_NCLK1_PAsSource = 1
278 ],
279 /// Bypass the PLL.
280 BYPASS OFFSET(16) NUMBITS(1) [],
281 /// Enable the PLL providing the ENET2 reference clock
282 ENET2_REF_EN OFFSET(20) NUMBITS(1) [],
283 /// Enable the PLL providing ENET 25 MHz reference clock
284 ENET_25M_REF_EN OFFSET(21) NUMBITS(1) [],
285 /// 1 - PLL is currently locked; 0 - PLL is not currently locked.
286 LOCK OFFSET(31) NUMBITS(1) []
287 ],
288 PFD_480 [
289 /// This field controls the fractional divide value
290 PFD0_FRAC OFFSET(0) NUMBITS(6) [],
291 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
292 PFD0_STABLE OFFSET(6) NUMBITS(1) [],
293 /// If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power
294 PFD0_CLKGATE OFFSET(7) NUMBITS(1) [],
295 /// This field controls the fractional divide value
296 PFD1_FRAC OFFSET(8) NUMBITS(6) [],
297 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
298 PFD1_STABLE OFFSET(14) NUMBITS(1) [],
299 /// IO Clock Gate
300 PFD1_CLKGATE OFFSET(15) NUMBITS(1) [],
301 /// This field controls the fractional divide value
302 PFD2_FRAC OFFSET(16) NUMBITS(6) [],
303 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
304 PFD2_STABLE OFFSET(22) NUMBITS(1) [],
305 /// IO Clock Gate
306 PFD2_CLKGATE OFFSET(23) NUMBITS(1) [],
307 /// This field controls the fractional divide value
308 PFD3_FRAC OFFSET(24) NUMBITS(6) [],
309 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
310 PFD3_STABLE OFFSET(30) NUMBITS(1) [],
311 /// IO Clock Gate
312 PFD3_CLKGATE OFFSET(31) NUMBITS(1) []
313 ],
314 PFD_528 [
315 /// This field controls the fractional divide value
316 PFD0_FRAC OFFSET(0) NUMBITS(6) [],
317 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
318 PFD0_STABLE OFFSET(6) NUMBITS(1) [],
319 /// If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power
320 PFD0_CLKGATE OFFSET(7) NUMBITS(1) [],
321 /// This field controls the fractional divide value
322 PFD1_FRAC OFFSET(8) NUMBITS(6) [],
323 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
324 PFD1_STABLE OFFSET(14) NUMBITS(1) [],
325 /// IO Clock Gate
326 PFD1_CLKGATE OFFSET(15) NUMBITS(1) [],
327 /// This field controls the fractional divide value
328 PFD2_FRAC OFFSET(16) NUMBITS(6) [],
329 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
330 PFD2_STABLE OFFSET(22) NUMBITS(1) [],
331 /// IO Clock Gate
332 PFD2_CLKGATE OFFSET(23) NUMBITS(1) [],
333 /// This field controls the fractional divide value
334 PFD3_FRAC OFFSET(24) NUMBITS(6) [],
335 /// This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional div
336 PFD3_STABLE OFFSET(30) NUMBITS(1) [],
337 /// IO Clock Gate
338 PFD3_CLKGATE OFFSET(31) NUMBITS(1) []
339 ],
340 MISC0 [
341 /// Control bit to power-down the analog bandgap reference circuitry
342 REFTOP_PWD OFFSET(0) NUMBITS(1) [],
343 /// Control bit to disable the self-bias circuit in the analog bandgap
344 REFTOP_SELFBIASOFF OFFSET(3) NUMBITS(1) [
345 /// Uses coarse bias currents for startup
346 UsesCoarseBiasCurrentsForStartup = 0,
347 /// Uses bandgap-based bias currents for best performance.
348 UsesBandgapBasedBiasCurrentsForBestPerformance = 1
349 ],
350 /// Not related to CCM. See Power Management Unit (PMU)
351 REFTOP_VBGADJ OFFSET(4) NUMBITS(3) [],
352 /// Status bit that signals the analog bandgap voltage is up and stable
353 REFTOP_VBGUP OFFSET(7) NUMBITS(1) [],
354 /// Configure the analog behavior in stop mode.
355 STOP_MODE_CONFIG OFFSET(10) NUMBITS(2) [
356 /// All analog except RTC powered down on stop mode assertion.
357 AllAnalogExceptRTCPoweredDownOnStopModeAssertion = 0,
358 /// Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
359 BesideRTCAnalogBandgap1p1And2p5RegulatorsAreAlsoOn = 1,
360 /// Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so
361 STOP_MODE_CONFIG_2 = 2,
362 /// Beside RTC, low-power bandgap is selected and the rest analog is powered down.
363 BesideRTCLowPowerBandgapIsSelectedAndTheRestAnalogIsPoweredDown = 3
364 ],
365 /// This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
366 DISCON_HIGH_SNVS OFFSET(12) NUMBITS(1) [
367 /// Turn on the switch
368 TurnOnTheSwitch = 0,
369 /// Turn off the switch
370 TurnOffTheSwitch = 1
371 ],
372 /// This field determines the bias current in the 24MHz oscillator
373 OSC_I OFFSET(13) NUMBITS(2) [
374 /// Nominal
375 Nominal = 0,
376 /// Decrease current by 12.5%
377 DecreaseCurrentBy125 = 1,
378 /// Decrease current by 25.0%
379 DecreaseCurrentBy250 = 2,
380 /// Decrease current by 37.5%
381 DecreaseCurrentBy375 = 3
382 ],
383 /// Status bit that signals that the output of the 24-MHz crystal oscillator is stab
384 OSC_XTALOK OFFSET(15) NUMBITS(1) [],
385 /// This bit enables the detector that signals when the 24MHz crystal oscillator is
386 OSC_XTALOK_EN OFFSET(16) NUMBITS(1) [],
387 /// This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clo
388 CLKGATE_CTRL OFFSET(25) NUMBITS(1) [
389 /// Allow the logic to automatically gate the clock when the XTAL is powered down.
390 AllowTheLogicToAutomaticallyGateTheClockWhenTheXTALIsPoweredDown = 0,
391 /// Prevent the logic from ever gating off the clock.
392 PreventTheLogicFromEverGatingOffTheClock = 1
393 ],
394 /// This field specifies the delay between powering up the XTAL 24MHz clock and rele
395 CLKGATE_DELAY OFFSET(26) NUMBITS(3) [
396 /// 0.5ms
397 _05ms = 0,
398 /// 1.0ms
399 _10ms = 1,
400 /// 2.0ms
401 _20ms = 2,
402 /// 3.0ms
403 _30ms = 3,
404 /// 4.0ms
405 _40ms = 4,
406 /// 5.0ms
407 _50ms = 5,
408 /// 6.0ms
409 _60ms = 6,
410 /// 7.0ms
411 _70ms = 7
412 ],
413 /// This field indicates which chip source is being used for the rtc clock
414 RTC_XTAL_SOURCE OFFSET(29) NUMBITS(1) [
415 /// Internal ring oscillator
416 InternalRingOscillator = 0,
417 /// RTC_XTAL
418 RTC_XTAL = 1
419 ],
420 /// This field powers down the 24M crystal oscillator if set true
421 XTAL_24M_PWD OFFSET(30) NUMBITS(1) []
422 ],
423 MISC1 [
424 /// This field selects the clk to be routed to anaclk1/1b.
425 LVDS1_CLK_SEL OFFSET(0) NUMBITS(5) [
426 /// Arm PLL
427 ArmPLL = 0,
428 /// System PLL
429 SystemPLL = 1,
430 /// ref_pfd4_clk == pll2_pfd0_clk
431 Ref_pfd4_clkPll2_pfd0_clk = 2,
432 /// ref_pfd5_clk == pll2_pfd1_clk
433 Ref_pfd5_clkPll2_pfd1_clk = 3,
434 /// ref_pfd6_clk == pll2_pfd2_clk
435 Ref_pfd6_clkPll2_pfd2_clk = 4,
436 /// ref_pfd7_clk == pll2_pfd3_clk
437 Ref_pfd7_clkPll2_pfd3_clk = 5,
438 /// Audio PLL
439 AudioPLL = 6,
440 /// Video PLL
441 VideoPLL = 7,
442 /// ethernet ref clock (ENET_PLL)
443 EthernetRefClockENET_PLL = 9,
444 /// USB1 PLL clock
445 USB1PLLClock = 12,
446 /// USB2 PLL clock
447 USB2PLLClock = 13,
448 /// ref_pfd0_clk == pll3_pfd0_clk
449 Ref_pfd0_clkPll3_pfd0_clk = 14,
450 /// ref_pfd1_clk == pll3_pfd1_clk
451 Ref_pfd1_clkPll3_pfd1_clk = 15,
452 /// ref_pfd2_clk == pll3_pfd2_clk
453 Ref_pfd2_clkPll3_pfd2_clk = 16,
454 /// ref_pfd3_clk == pll3_pfd3_clk
455 Ref_pfd3_clkPll3_pfd3_clk = 17,
456 /// xtal (24M)
457 Xtal24M = 18
458 ],
459 /// This enables the LVDS output buffer for anaclk1/1b
460 LVDSCLK1_OBEN OFFSET(10) NUMBITS(1) [],
461 /// This enables the LVDS input buffer for anaclk1/1b
462 LVDSCLK1_IBEN OFFSET(12) NUMBITS(1) [],
463 /// This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the
464 PFD_480_AUTOGATE_EN OFFSET(16) NUMBITS(1) [],
465 /// This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the
466 PFD_528_AUTOGATE_EN OFFSET(17) NUMBITS(1) [],
467 /// This status bit is set to one when the temperature sensor panic interrupt assert
468 IRQ_TEMPPANIC OFFSET(27) NUMBITS(1) [],
469 /// This status bit is set to one when the temperature sensor low interrupt asserts
470 IRQ_TEMPLOW OFFSET(28) NUMBITS(1) [],
471 /// This status bit is set to one when the temperature sensor high interrupt asserts
472 IRQ_TEMPHIGH OFFSET(29) NUMBITS(1) [],
473 /// This status bit is set to one when when any of the analog regulator brownout int
474 IRQ_ANA_BO OFFSET(30) NUMBITS(1) [],
475 /// This status bit is set to one when when any of the digital regulator brownout in
476 IRQ_DIG_BO OFFSET(31) NUMBITS(1) []
477 ],
478 MISC2 [
479 /// This field defines the brown out voltage offset for the CORE power domain
480 REG0_BO_OFFSET OFFSET(0) NUMBITS(3) [
481 /// Brownout offset = 0.100V
482 BrownoutOffset0100V = 4,
483 /// Brownout offset = 0.175V
484 BrownoutOffset0175V = 7
485 ],
486 /// Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)
487 REG0_BO_STATUS OFFSET(3) NUMBITS(1) [
488 /// Brownout, supply is below target minus brownout offset.
489 BrownoutSupplyIsBelowTargetMinusBrownoutOffset = 1
490 ],
491 /// Enables the brownout detection.Not related to CCM. See Power Management Unit (PM
492 REG0_ENABLE_BO OFFSET(5) NUMBITS(1) [],
493 /// ARM supply Not related to CCM. See Power Management Unit (PMU)
494 REG0_OK OFFSET(6) NUMBITS(1) [],
495 /// When USB is in low power suspend mode this Control bit is used to indicate if ot
496 PLL3_DISABLE OFFSET(7) NUMBITS(1) [
497 /// PLL3 is being used by peripherals and is enabled when SoC is not in any low powe
498 PLL3IsBeingUsedByPeripheralsAndIsEnabledWhenSoCIsNotInAnyLowPowerMode = 0,
499 /// PLL3 can be disabled when the SoC is not in any low power mode
500 PLL3CanBeDisabledWhenTheSoCIsNotInAnyLowPowerMode = 1
501 ],
502 /// This field defines the brown out voltage offset for the xPU power domain
503 REG1_BO_OFFSET OFFSET(8) NUMBITS(3) [
504 /// Brownout offset = 0.100V
505 BrownoutOffset0100V = 4,
506 /// Brownout offset = 0.175V
507 BrownoutOffset0175V = 7
508 ],
509 /// Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)
510 REG1_BO_STATUS OFFSET(11) NUMBITS(1) [
511 /// Brownout, supply is below target minus brownout offset.
512 BrownoutSupplyIsBelowTargetMinusBrownoutOffset = 1
513 ],
514 /// Enables the brownout detection.Not related to CCM. See Power Management Unit (PM
515 REG1_ENABLE_BO OFFSET(13) NUMBITS(1) [],
516 /// GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)
517 REG1_OK OFFSET(14) NUMBITS(1) [],
518 /// LSB of Post-divider for Audio PLL
519 AUDIO_DIV_LSB OFFSET(15) NUMBITS(1) [
520 /// divide by 1 (Default)
521 DivideBy1Default = 0,
522 /// divide by 2
523 DivideBy2 = 1
524 ],
525 /// This field defines the brown out voltage offset for the xPU power domain
526 REG2_BO_OFFSET OFFSET(16) NUMBITS(3) [
527 /// Brownout offset = 0.100V
528 BrownoutOffset0100V = 4,
529 /// Brownout offset = 0.175V
530 BrownoutOffset0175V = 7
531 ],
532 /// Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)
533 REG2_BO_STATUS OFFSET(19) NUMBITS(1) [],
534 /// Enables the brownout detection.Not related to CCM. See Power Management Unit (PM
535 REG2_ENABLE_BO OFFSET(21) NUMBITS(1) [],
536 /// Signals that the voltage is above the brownout level for the SOC supply
537 REG2_OK OFFSET(22) NUMBITS(1) [],
538 /// MSB of Post-divider for Audio PLL
539 AUDIO_DIV_MSB OFFSET(23) NUMBITS(1) [
540 /// divide by 1 (Default)
541 DivideBy1Default = 0,
542 /// divide by 2
543 DivideBy2 = 1
544 ],
545 /// Number of clock periods (24MHz clock).Not related to CCM. See Power Management U
546 REG0_STEP_TIME OFFSET(24) NUMBITS(2) [
547 /// 64
548 _64 = 0,
549 /// 128
550 _128 = 1,
551 /// 256
552 _256 = 2,
553 /// 512
554 _512 = 3
555 ],
556 /// Number of clock periods (24MHz clock).Not related to CCM. See Power Management U
557 REG1_STEP_TIME OFFSET(26) NUMBITS(2) [
558 /// 64
559 _64 = 0,
560 /// 128
561 _128 = 1,
562 /// 256
563 _256 = 2,
564 /// 512
565 _512 = 3
566 ],
567 /// Number of clock periods (24MHz clock).Not related to CCM. See Power Management U
568 REG2_STEP_TIME OFFSET(28) NUMBITS(2) [
569 /// 64
570 _64 = 0,
571 /// 128
572 _128 = 1,
573 /// 256
574 _256 = 2,
575 /// 512
576 _512 = 3
577 ],
578 /// Post-divider for video
579 VIDEO_DIV OFFSET(30) NUMBITS(2) [
580 /// divide by 1 (Default)
581 DivideBy1Default = 0,
582 /// divide by 2
583 DivideBy2 = 1,
584 /// divide by 1
585 DivideBy1 = 2,
586 /// divide by 4
587 DivideBy4 = 3
588 ]
589 ]
590];
591
592const CCM_ANALOG_BASE: StaticRef<CcmAnalogRegisters> =
593 unsafe { StaticRef::new(0x400D8000 as *const CcmAnalogRegisters) };
594
595pub struct CcmAnalog {
596 registers: StaticRef<CcmAnalogRegisters>,
597}
598
599impl CcmAnalog {
600 /// Creates a new `CcmAnalog` peripheral
601 pub const fn new() -> Self {
602 Self {
603 registers: CCM_ANALOG_BASE,
604 }
605 }
606
607 /// Returns the PLL1 `DIV_SEL` value
608 pub fn pll1_div_sel(&self) -> u32 {
609 self.registers.pll_arm.reg.read(PLL_ARM::DIV_SELECT)
610 }
611
612 /// Restart PLL1 using the new `div_sel`
613 ///
614 /// Clamps `div_sel` to [54, 108].
615 pub fn restart_pll1(&self, div_sel: u32) {
616 let div_sel = div_sel.min(108).max(54);
617
618 // Clear all bits except powerdown
619 self.registers.pll_arm.reg.write(PLL_ARM::POWERDOWN::SET);
620 // Clear powerdown write above
621 self.registers
622 .pll_arm
623 .reg
624 .write(PLL_ARM::DIV_SELECT.val(div_sel));
625 // Enable the PLL
626 self.registers.pll_arm.set.write(PLL_ARM::ENABLE::SET);
627 // Wait for lock
628 while self.registers.pll_arm.reg.read(PLL_ARM::LOCK) == 0 {}
629 }
630}