msp432/
lib.rs

Help
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5#![no_std]
6
7use cortexm4::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM4, CortexMVariant};
8
9pub mod adc;
10pub mod chip;
11pub mod cs;
12pub mod dma;
13pub mod flctl;
14pub mod gpio;
15pub mod i2c;
16pub mod nvic;
17pub mod pcm;
18pub mod ref_module;
19pub mod sysctl;
20pub mod timer;
21pub mod uart;
22pub mod usci;
23pub mod wdt;
24
25extern "C" {
26    // _estack is not really a function, but it makes the types work
27    // You should never actually invoke it!!
28    fn _estack();
29}
30
31#[cfg_attr(
32    all(target_arch = "arm", target_os = "none"),
33    link_section = ".vectors"
34)]
35// used Ensures that the symbol is kept until the final binary
36#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
37pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
38    _estack,
39    initialize_ram_jump_to_main,
40    unhandled_interrupt,          // NMI
41    CortexM4::HARD_FAULT_HANDLER, // Hard Fault
42    unhandled_interrupt,          // MemManage
43    unhandled_interrupt,          // BusFault
44    unhandled_interrupt,          // UsageFault
45    unhandled_interrupt,
46    unhandled_interrupt,
47    unhandled_interrupt,
48    unhandled_interrupt,
49    CortexM4::SVC_HANDLER, // SVC
50    unhandled_interrupt,   // DebugMon
51    unhandled_interrupt,
52    unhandled_interrupt,       // PendSV
53    CortexM4::SYSTICK_HANDLER, // SysTick
54];
55
56#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
57// used Ensures that the symbol is kept until the final binary
58#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
59pub static IRQS: [unsafe extern "C" fn(); 64] = [
60    CortexM4::GENERIC_ISR, // Power Supply System (PSS) (0)
61    CortexM4::GENERIC_ISR, // Clock System (CS) (1)
62    CortexM4::GENERIC_ISR, // Power Control Manager (PCM) (2)
63    CortexM4::GENERIC_ISR, // Watchdog Timer A (WDT_A) (3)
64    CortexM4::GENERIC_ISR, // FPU_INT, Combined interrupt from flags in FPSCR (4)
65    CortexM4::GENERIC_ISR, // FLash Controller (FLCTL) (5)
66    CortexM4::GENERIC_ISR, // Comparator E0 (6)
67    CortexM4::GENERIC_ISR, // Comparator E1 (7)
68    CortexM4::GENERIC_ISR, // Timer A0 TA0CCTL0.CCIFG (8)
69    CortexM4::GENERIC_ISR, // Timer A0 TA0CCTLx.CCIFG (x = 1 to 4), TA0CTL.TAIFG (9)
70    CortexM4::GENERIC_ISR, // Timer A1 TA1CCTL0.CCIFG (10)
71    CortexM4::GENERIC_ISR, // Timer A1 TA1CCTLx.CCIFG (x = 1 to 4), TA1CTL.TAIFG (11)
72    CortexM4::GENERIC_ISR, // Timer A2 TA2CCTL0.CCIFG (12)
73    CortexM4::GENERIC_ISR, // Timer A2 TA2CCTLx.CCIFG (x = 1 to 4), TA2CTL.TAIFG (13)
74    CortexM4::GENERIC_ISR, // Timer A3 TA3CCTL0.CCIFG (13)
75    CortexM4::GENERIC_ISR, // Timer A3 TA3CCTLx.CCIFG (x = 1 to 4), TA3CTL.TAIFG (15)
76    CortexM4::GENERIC_ISR, // eUSCI A0 (16)
77    CortexM4::GENERIC_ISR, // eUSCI A1 (17)
78    CortexM4::GENERIC_ISR, // eUSCI A2 (18)
79    CortexM4::GENERIC_ISR, // eUSCI A3 (19)
80    CortexM4::GENERIC_ISR, // eUSCI B0 (20)
81    CortexM4::GENERIC_ISR, // eUSCI B1 (21)
82    CortexM4::GENERIC_ISR, // eUSCI B2 (22)
83    CortexM4::GENERIC_ISR, // eUSCI B3 (23)
84    CortexM4::GENERIC_ISR, // Precision ADC (24)
85    CortexM4::GENERIC_ISR, // Timer32 INT1 (25)
86    CortexM4::GENERIC_ISR, // Timer32 INT2 (26)
87    CortexM4::GENERIC_ISR, // Timer32 combined interrupt (27)
88    CortexM4::GENERIC_ISR, // AES256 (28)
89    CortexM4::GENERIC_ISR, // RTC_C (29)
90    CortexM4::GENERIC_ISR, // DMA error (30)
91    CortexM4::GENERIC_ISR, // DMA INT3 (31)
92    CortexM4::GENERIC_ISR, // DMA INT2 (32)
93    CortexM4::GENERIC_ISR, // DMA INT1 (33)
94    CortexM4::GENERIC_ISR, // DMA INT0 (34)
95    CortexM4::GENERIC_ISR, // IO Port 1 (35)
96    CortexM4::GENERIC_ISR, // IO Port 2 (36)
97    CortexM4::GENERIC_ISR, // IO Port 3 (37)
98    CortexM4::GENERIC_ISR, // IO Port 4 (38)
99    CortexM4::GENERIC_ISR, // IO Port 5 (39)
100    CortexM4::GENERIC_ISR, // IO Port 6 (40)
101    unhandled_interrupt,   // Reserved (41)
102    unhandled_interrupt,   // Reserved (42)
103    unhandled_interrupt,   // Reserved (43)
104    unhandled_interrupt,   // Reserved (44)
105    unhandled_interrupt,   // Reserved (45)
106    unhandled_interrupt,   // Reserved (46)
107    unhandled_interrupt,   // Reserved (47)
108    unhandled_interrupt,   // Reserved (48)
109    unhandled_interrupt,   // Reserved (49)
110    unhandled_interrupt,   // Reserved (50)
111    unhandled_interrupt,   // Reserved (51)
112    unhandled_interrupt,   // Reserved (52)
113    unhandled_interrupt,   // Reserved (53)
114    unhandled_interrupt,   // Reserved (54)
115    unhandled_interrupt,   // Reserved (55)
116    unhandled_interrupt,   // Reserved (56)
117    unhandled_interrupt,   // Reserved (57)
118    unhandled_interrupt,   // Reserved (58)
119    unhandled_interrupt,   // Reserved (59)
120    unhandled_interrupt,   // Reserved (60)
121    unhandled_interrupt,   // Reserved (61)
122    unhandled_interrupt,   // Reserved (62)
123    unhandled_interrupt,   // Reserved (63)
124];
125
126pub unsafe fn init() {
127    cortexm4::nvic::disable_all();
128    cortexm4::nvic::clear_all_pending();
129    cortexm4::nvic::enable_all();
130}
msp432/lib.rs

msp432/
lib.rs
