1use kernel::utilities::registers::{
6 interfaces::{ReadWriteable, Readable, Writeable},
7 register_bitfields, register_structs, ReadWrite,
8};
9use kernel::utilities::StaticRef;
10
11register_structs! {
12 PeriRegisters {
13 (0x000 => _reserved0),
14 (0x200 => timeout_ctl: ReadWrite<u32>),
15 (0x204 => _reserved1),
16 (0x220 => tr_cmd: ReadWrite<u32, TR_CMD::Register>),
17 (0x224 => _reserved2),
18 (0x400 => div_cmd: ReadWrite<u32, DIV_CMD::Register>),
19 (0x404 => _reserved3),
20 (0xC00 => clock_ctl_0: ReadWrite<u32, CLOCK_CTL::Register>),
21 (0xC04 => clock_ctl_1: ReadWrite<u32, CLOCK_CTL::Register>),
22 (0xC08 => clock_ctl_2: ReadWrite<u32, CLOCK_CTL::Register>),
23 (0xC0C => clock_ctl_3: ReadWrite<u32, CLOCK_CTL::Register>),
24 (0xC10 => clock_ctl_4: ReadWrite<u32, CLOCK_CTL::Register>),
25 (0xC14 => clock_ctl_5: ReadWrite<u32, CLOCK_CTL::Register>),
26 (0xC18 => clock_ctl_6: ReadWrite<u32, CLOCK_CTL::Register>),
27 (0xC1C => clock_ctl_7: ReadWrite<u32, CLOCK_CTL::Register>),
28 (0xC20 => clock_ctl_8: ReadWrite<u32, CLOCK_CTL::Register>),
29 (0xC24 => clock_ctl_9: ReadWrite<u32, CLOCK_CTL::Register>),
30 (0xC28 => clock_ctl_10: ReadWrite<u32, CLOCK_CTL::Register>),
31 (0xC2C => clock_ctl_11: ReadWrite<u32, CLOCK_CTL::Register>),
32 (0xC30 => clock_ctl_12: ReadWrite<u32, CLOCK_CTL::Register>),
33 (0xC34 => clock_ctl_13: ReadWrite<u32, CLOCK_CTL::Register>),
34 (0xC38 => clock_ctl_14: ReadWrite<u32, CLOCK_CTL::Register>),
35 (0xC3C => clock_ctl_15: ReadWrite<u32, CLOCK_CTL::Register>),
36 (0xC40 => clock_ctl_16: ReadWrite<u32, CLOCK_CTL::Register>),
37 (0xC44 => clock_ctl_17: ReadWrite<u32, CLOCK_CTL::Register>),
38 (0xC48 => clock_ctl_18: ReadWrite<u32, CLOCK_CTL::Register>),
39 (0xC4C => clock_ctl_19: ReadWrite<u32, CLOCK_CTL::Register>),
40 (0xC50 => clock_ctl_20: ReadWrite<u32, CLOCK_CTL::Register>),
41 (0xC54 => clock_ctl_21: ReadWrite<u32, CLOCK_CTL::Register>),
42 (0xC58 => clock_ctl_22: ReadWrite<u32, CLOCK_CTL::Register>),
43 (0xC5C => clock_ctl_23: ReadWrite<u32, CLOCK_CTL::Register>),
44 (0xC60 => clock_ctl_24: ReadWrite<u32, CLOCK_CTL::Register>),
45 (0xC64 => clock_ctl_25: ReadWrite<u32, CLOCK_CTL::Register>),
46 (0xC68 => clock_ctl_26: ReadWrite<u32, CLOCK_CTL::Register>),
47 (0xC6C => clock_ctl_27: ReadWrite<u32, CLOCK_CTL::Register>),
48 (0xC70 => clock_ctl_28: ReadWrite<u32, CLOCK_CTL::Register>),
49 (0xC74 => clock_ctl_29: ReadWrite<u32, CLOCK_CTL::Register>),
50 (0xC78 => clock_ctl_30: ReadWrite<u32, CLOCK_CTL::Register>),
51 (0xC7C => clock_ctl_31: ReadWrite<u32, CLOCK_CTL::Register>),
52 (0xC80 => clock_ctl_32: ReadWrite<u32, CLOCK_CTL::Register>),
53 (0xC84 => clock_ctl_33: ReadWrite<u32, CLOCK_CTL::Register>),
54 (0xC88 => clock_ctl_34: ReadWrite<u32, CLOCK_CTL::Register>),
55 (0xC8C => clock_ctl_35: ReadWrite<u32, CLOCK_CTL::Register>),
56 (0xC90 => clock_ctl_36: ReadWrite<u32, CLOCK_CTL::Register>),
57 (0xC94 => clock_ctl_37: ReadWrite<u32, CLOCK_CTL::Register>),
58 (0xC98 => clock_ctl_38: ReadWrite<u32, CLOCK_CTL::Register>),
59 (0xC9C => clock_ctl_39: ReadWrite<u32, CLOCK_CTL::Register>),
60 (0xCA0 => clock_ctl_40: ReadWrite<u32, CLOCK_CTL::Register>),
61 (0xCA4 => clock_ctl_41: ReadWrite<u32, CLOCK_CTL::Register>),
62 (0xCA8 => clock_ctl_42: ReadWrite<u32, CLOCK_CTL::Register>),
63 (0xCAC => clock_ctl_43: ReadWrite<u32, CLOCK_CTL::Register>),
64 (0xCB0 => clock_ctl_44: ReadWrite<u32, CLOCK_CTL::Register>),
65 (0xCB4 => clock_ctl_45: ReadWrite<u32, CLOCK_CTL::Register>),
66 (0xCB8 => clock_ctl_46: ReadWrite<u32, CLOCK_CTL::Register>),
67 (0xCBC => clock_ctl_47: ReadWrite<u32, CLOCK_CTL::Register>),
68 (0xCC0 => clock_ctl_48: ReadWrite<u32, CLOCK_CTL::Register>),
69 (0xCC4 => clock_ctl_49: ReadWrite<u32, CLOCK_CTL::Register>),
70 (0xCC8 => clock_ctl_50: ReadWrite<u32, CLOCK_CTL::Register>),
71 (0xCCC => clock_ctl_51: ReadWrite<u32, CLOCK_CTL::Register>),
72 (0xCD0 => clock_ctl_52: ReadWrite<u32, CLOCK_CTL::Register>),
73 (0xCD4 => clock_ctl_53: ReadWrite<u32, CLOCK_CTL::Register>),
74 (0xCD8 => _reserved4),
75 (0x1000 => div_8_ctl_0: ReadWrite<u32, DIV_8_CTL::Register>),
76 (0x1004 => div_8_ctl_1: ReadWrite<u32, DIV_8_CTL::Register>),
77 (0x1008 => div_8_ctl_2: ReadWrite<u32, DIV_8_CTL::Register>),
78 (0x100C => div_8_ctl_3: ReadWrite<u32, DIV_8_CTL::Register>),
79 (0x1010 => div_8_ctl_4: ReadWrite<u32, DIV_8_CTL::Register>),
80 (0x1014 => div_8_ctl_5: ReadWrite<u32, DIV_8_CTL::Register>),
81 (0x1018 => div_8_ctl_6: ReadWrite<u32, DIV_8_CTL::Register>),
82 (0x101C => div_8_ctl_7: ReadWrite<u32, DIV_8_CTL::Register>),
83 (0x1020 => _reserved5),
84 (0x1400 => div_16_ctl_0: ReadWrite<u32, DIV_16_CTL::Register>),
85 (0x1404 => div_16_ctl_1: ReadWrite<u32, DIV_16_CTL::Register>),
86 (0x1408 => div_16_ctl_2: ReadWrite<u32, DIV_16_CTL::Register>),
87 (0x140C => div_16_ctl_3: ReadWrite<u32, DIV_16_CTL::Register>),
88 (0x1410 => div_16_ctl_4: ReadWrite<u32, DIV_16_CTL::Register>),
89 (0x1414 => div_16_ctl_5: ReadWrite<u32, DIV_16_CTL::Register>),
90 (0x1418 => div_16_ctl_6: ReadWrite<u32, DIV_16_CTL::Register>),
91 (0x141C => div_16_ctl_7: ReadWrite<u32, DIV_16_CTL::Register>),
92 (0x1420 => div_16_ctl_8: ReadWrite<u32, DIV_16_CTL::Register>),
93 (0x1424 => div_16_ctl_9: ReadWrite<u32, DIV_16_CTL::Register>),
94 (0x1428 => div_16_ctl_10: ReadWrite<u32, DIV_16_CTL::Register>),
95 (0x142C => div_16_ctl_11: ReadWrite<u32, DIV_16_CTL::Register>),
96 (0x1430 => div_16_ctl_12: ReadWrite<u32, DIV_16_CTL::Register>),
97 (0x1434 => div_16_ctl_13: ReadWrite<u32, DIV_16_CTL::Register>),
98 (0x1438 => div_16_ctl_14: ReadWrite<u32, DIV_16_CTL::Register>),
99 (0x143C => div_16_ctl_15: ReadWrite<u32, DIV_16_CTL::Register>),
100 (0x1440 => _reserved6),
101 (0x1800 => div_16_5_ctl_0: ReadWrite<u32, DIV_16_5_CTL::Register>),
102 (0x1804 => div_16_5_ctl_1: ReadWrite<u32, DIV_16_5_CTL::Register>),
103 (0x1808 => div_16_5_ctl_2: ReadWrite<u32, DIV_16_5_CTL::Register>),
104 (0x180C => div_16_5_ctl_3: ReadWrite<u32, DIV_16_5_CTL::Register>),
105 (0x1810 => _reserved7),
106 (0x1C00 => div_24_5_ctl_0: ReadWrite<u32, DIV_24_5_CTL::Register>),
107 (0x1C04 => _reserved8),
108 (0x2000 => ecc_ctl: ReadWrite<u32, ECC_CTL::Register>),
109 (0x2004 => @END),
110 }
111}
112register_bitfields![u32,
113TIMEOUT_CTL [
114 TIMEOUT OFFSET(0) NUMBITS(16) []
115],
116TR_CMD [
117 TR_SEL OFFSET(0) NUMBITS(8) [],
118 GROUP_SEL OFFSET(8) NUMBITS(5) [],
119 TR_EDGE OFFSET(29) NUMBITS(1) [],
120 OUT_SEL OFFSET(30) NUMBITS(1) [],
121 ACTIVATE OFFSET(31) NUMBITS(1) []
122],
123DIV_CMD [
124 DIV_SEL OFFSET(0) NUMBITS(8) [],
125 TYPE_SEL OFFSET(8) NUMBITS(2) [
126 DIV8_0 = 0b00,
127 DIV16_0 = 0b01,
128 DIV16_5 = 0b10,
129 DIV24_5 = 0b11,
130 ],
131 PA_DIV_SEL OFFSET(16) NUMBITS(8) [],
132 PA_TYPE_SEL OFFSET(24) NUMBITS(2) [
133 DIV8_0 = 0b00,
134 DIV16_0 = 0b01,
135 DIV16_5 = 0b10,
136 DIV24_5 = 0b11,
137 ],
138 DISABLE OFFSET(30) NUMBITS(1) [],
139 ENABLE OFFSET(31) NUMBITS(1) []
140],
141ECC_CTL [
142 WORD_ADDR OFFSET(0) NUMBITS(11) [],
143 ECC_EN OFFSET(16) NUMBITS(1) [],
144 ECC_INJ_EN OFFSET(18) NUMBITS(1) [],
145 PARITY OFFSET(24) NUMBITS(8) []
146],
147CLOCK_CTL [
148 DIV_SEL OFFSET(0) NUMBITS(8) [],
149 TYPE_SEL OFFSET(8) NUMBITS(2) [
150 DIV8_0 = 0b00,
151 DIV16_0 = 0b01,
152 DIV16_5 = 0b10,
153 DIV24_5 = 0b11,
154 ]
155],
156DIV_8_CTL [
157 EN OFFSET(0) NUMBITS(1) [],
158 INT8_DIV OFFSET(8) NUMBITS(8) []
159],
160DIV_16_CTL [
161 EN OFFSET(0) NUMBITS(1) [],
162 INT16_DIV OFFSET(8) NUMBITS(16) []
163],
164DIV_16_5_CTL [
165 EN OFFSET(0) NUMBITS(1) [],
166 FRAC5_DIV OFFSET(3) NUMBITS(5) [],
167 INT16_DIV OFFSET(8) NUMBITS(16) []
168],
169DIV_24_5_CTL [
170 EN OFFSET(0) NUMBITS(1) [],
171 FRAC5_DIV OFFSET(3) NUMBITS(5) [],
172 INT24_DIV OFFSET(8) NUMBITS(24) []
173],
174];
175const PERI_BASE: StaticRef<PeriRegisters> =
176 unsafe { StaticRef::new(0x40000000 as *const PeriRegisters) };
177
178pub struct Peri {
179 registers: StaticRef<PeriRegisters>,
180}
181
182impl Peri {
183 pub const fn new() -> Peri {
184 Peri {
185 registers: PERI_BASE,
186 }
187 }
188
189 pub fn init_uart_clock(&self) {
190 self.registers
191 .div_cmd
192 .write(DIV_CMD::DISABLE::SET + DIV_CMD::DIV_SEL.val(3) + DIV_CMD::TYPE_SEL::DIV16_5);
193 self.registers
194 .div_16_5_ctl_3
195 .modify(DIV_16_5_CTL::INT16_DIV.val(3) + DIV_16_5_CTL::FRAC5_DIV.val(20));
196 self.registers.div_cmd.write(
197 DIV_CMD::ENABLE::SET
198 + DIV_CMD::DIV_SEL.val(3)
199 + DIV_CMD::TYPE_SEL::DIV16_5
200 + DIV_CMD::PA_TYPE_SEL.val(3)
201 + DIV_CMD::PA_DIV_SEL.val(255),
202 );
203
204 while self.registers.div_cmd.read(DIV_CMD::ENABLE) == 1 {}
205
206 self.registers
207 .clock_ctl_5
208 .modify(CLOCK_CTL::DIV_SEL.val(3) + CLOCK_CTL::TYPE_SEL::DIV16_5);
209 }
210
211 pub fn init_alarm_clock(&self) {
212 self.registers
213 .div_cmd
214 .write(DIV_CMD::DISABLE::SET + DIV_CMD::DIV_SEL.val(0) + DIV_CMD::TYPE_SEL::DIV8_0);
215 self.registers
216 .div_8_ctl_0
217 .modify(DIV_8_CTL::INT8_DIV.val(7));
218 self.registers.div_cmd.write(
219 DIV_CMD::ENABLE::SET
220 + DIV_CMD::DIV_SEL.val(0)
221 + DIV_CMD::TYPE_SEL::DIV8_0
222 + DIV_CMD::PA_TYPE_SEL.val(3)
223 + DIV_CMD::PA_DIV_SEL.val(255),
224 );
225
226 while self.registers.div_cmd.read(DIV_CMD::ENABLE) == 1 {}
227
228 self.registers
229 .clock_ctl_15
230 .modify(CLOCK_CTL::DIV_SEL.val(0) + CLOCK_CTL::TYPE_SEL::DIV8_0);
231 }
232}