lowrisc/registers/
sysrst_ctrl_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for sysrst_ctrl.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of keyboard combos
15pub const SYSRST_CTRL_PARAM_NUM_COMBO: u32 = 4;
16/// Number of timer bits
17pub const SYSRST_CTRL_PARAM_TIMER_WIDTH: u32 = 16;
18/// Number of detection timer bits
19pub const SYSRST_CTRL_PARAM_DET_TIMER_WIDTH: u32 = 32;
20/// Number of alerts
21pub const SYSRST_CTRL_PARAM_NUM_ALERTS: u32 = 1;
22/// Register width
23pub const SYSRST_CTRL_PARAM_REG_WIDTH: u32 = 32;
24
25register_structs! {
26    pub SysrstCtrlRegisters {
27        /// Interrupt State Register
28        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
29        /// Interrupt Enable Register
30        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
31        /// Interrupt Test Register
32        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
33        /// Alert Test Register
34        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
35        /// Configuration write enable control register
36        (0x0010 => pub(crate) regwen: ReadWrite<u32, REGWEN::Register>),
37        /// EC reset control register
38        (0x0014 => pub(crate) ec_rst_ctl: ReadWrite<u32, EC_RST_CTL::Register>),
39        /// Ultra low power AC debounce control register
40        (0x0018 => pub(crate) ulp_ac_debounce_ctl: ReadWrite<u32, ULP_AC_DEBOUNCE_CTL::Register>),
41        /// Ultra low power lid debounce control register
42        (0x001c => pub(crate) ulp_lid_debounce_ctl: ReadWrite<u32, ULP_LID_DEBOUNCE_CTL::Register>),
43        /// Ultra low power pwrb debounce control register
44        (0x0020 => pub(crate) ulp_pwrb_debounce_ctl: ReadWrite<u32, ULP_PWRB_DEBOUNCE_CTL::Register>),
45        /// Ultra low power control register
46        (0x0024 => pub(crate) ulp_ctl: ReadWrite<u32, ULP_CTL::Register>),
47        /// Ultra low power status
48        (0x0028 => pub(crate) ulp_status: ReadWrite<u32, ULP_STATUS::Register>),
49        /// wakeup status
50        (0x002c => pub(crate) wkup_status: ReadWrite<u32, WKUP_STATUS::Register>),
51        /// configure key input output invert property
52        (0x0030 => pub(crate) key_invert_ctl: ReadWrite<u32, KEY_INVERT_CTL::Register>),
53        /// This register determines which override values are allowed for a given output.
54        (0x0034 => pub(crate) pin_allowed_ctl: ReadWrite<u32, PIN_ALLOWED_CTL::Register>),
55        /// Enables the override function for a specific pin.
56        (0x0038 => pub(crate) pin_out_ctl: ReadWrite<u32, PIN_OUT_CTL::Register>),
57        /// Sets the pin override value. Note that only the values
58        (0x003c => pub(crate) pin_out_value: ReadWrite<u32, PIN_OUT_VALUE::Register>),
59        /// For SW to read the sysrst_ctrl inputs like GPIO
60        (0x0040 => pub(crate) pin_in_value: ReadWrite<u32, PIN_IN_VALUE::Register>),
61        /// Define the keys or inputs that can trigger the interrupt
62        (0x0044 => pub(crate) key_intr_ctl: ReadWrite<u32, KEY_INTR_CTL::Register>),
63        /// Debounce timer control register for key-triggered interrupt
64        (0x0048 => pub(crate) key_intr_debounce_ctl: ReadWrite<u32, KEY_INTR_DEBOUNCE_CTL::Register>),
65        /// Debounce timer control register for pwrb_in H2L transition
66        (0x004c => pub(crate) auto_block_debounce_ctl: ReadWrite<u32, AUTO_BLOCK_DEBOUNCE_CTL::Register>),
67        /// configure the key outputs to auto-override and their value
68        (0x0050 => pub(crate) auto_block_out_ctl: ReadWrite<u32, AUTO_BLOCK_OUT_CTL::Register>),
69        /// To define the keys that define the pre-condition of the combo
70        (0x0054 => pub(crate) com_pre_sel_ctl: [ReadWrite<u32, COM_PRE_SEL_CTL::Register>; 4]),
71        /// To define the duration that the combo pre-condition should be pressed
72        (0x0064 => pub(crate) com_pre_det_ctl: [ReadWrite<u32, COM_PRE_DET_CTL::Register>; 4]),
73        /// To define the keys that trigger the combo
74        (0x0074 => pub(crate) com_sel_ctl: [ReadWrite<u32, COM_SEL_CTL::Register>; 4]),
75        /// To define the duration that the combo should be pressed
76        (0x0084 => pub(crate) com_det_ctl: [ReadWrite<u32, COM_DET_CTL::Register>; 4]),
77        /// To define the actions once the combo is detected
78        (0x0094 => pub(crate) com_out_ctl: [ReadWrite<u32, COM_OUT_CTL::Register>; 4]),
79        /// Combo interrupt source. These registers will only be set if the
80        (0x00a4 => pub(crate) combo_intr_status: ReadWrite<u32, COMBO_INTR_STATUS::Register>),
81        /// key interrupt source
82        (0x00a8 => pub(crate) key_intr_status: ReadWrite<u32, KEY_INTR_STATUS::Register>),
83        (0x00ac => @END),
84    }
85}
86
87register_bitfields![u32,
88    /// Common Interrupt Offsets
89    pub(crate) INTR [
90        EVENT_DETECTED OFFSET(0) NUMBITS(1) [],
91    ],
92    pub(crate) ALERT_TEST [
93        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
94    ],
95    pub(crate) REGWEN [
96        WRITE_EN OFFSET(0) NUMBITS(1) [],
97    ],
98    pub(crate) EC_RST_CTL [
99        EC_RST_PULSE OFFSET(0) NUMBITS(16) [],
100    ],
101    pub(crate) ULP_AC_DEBOUNCE_CTL [
102        ULP_AC_DEBOUNCE_TIMER OFFSET(0) NUMBITS(16) [],
103    ],
104    pub(crate) ULP_LID_DEBOUNCE_CTL [
105        ULP_LID_DEBOUNCE_TIMER OFFSET(0) NUMBITS(16) [],
106    ],
107    pub(crate) ULP_PWRB_DEBOUNCE_CTL [
108        ULP_PWRB_DEBOUNCE_TIMER OFFSET(0) NUMBITS(16) [],
109    ],
110    pub(crate) ULP_CTL [
111        ULP_ENABLE OFFSET(0) NUMBITS(1) [],
112    ],
113    pub(crate) ULP_STATUS [
114        ULP_WAKEUP OFFSET(0) NUMBITS(1) [],
115    ],
116    pub(crate) WKUP_STATUS [
117        WAKEUP_STS OFFSET(0) NUMBITS(1) [],
118    ],
119    pub(crate) KEY_INVERT_CTL [
120        KEY0_IN OFFSET(0) NUMBITS(1) [],
121        KEY0_OUT OFFSET(1) NUMBITS(1) [],
122        KEY1_IN OFFSET(2) NUMBITS(1) [],
123        KEY1_OUT OFFSET(3) NUMBITS(1) [],
124        KEY2_IN OFFSET(4) NUMBITS(1) [],
125        KEY2_OUT OFFSET(5) NUMBITS(1) [],
126        PWRB_IN OFFSET(6) NUMBITS(1) [],
127        PWRB_OUT OFFSET(7) NUMBITS(1) [],
128        AC_PRESENT OFFSET(8) NUMBITS(1) [],
129        BAT_DISABLE OFFSET(9) NUMBITS(1) [],
130        LID_OPEN OFFSET(10) NUMBITS(1) [],
131        Z3_WAKEUP OFFSET(11) NUMBITS(1) [],
132    ],
133    pub(crate) PIN_ALLOWED_CTL [
134        BAT_DISABLE_0 OFFSET(0) NUMBITS(1) [],
135        EC_RST_L_0 OFFSET(1) NUMBITS(1) [],
136        PWRB_OUT_0 OFFSET(2) NUMBITS(1) [],
137        KEY0_OUT_0 OFFSET(3) NUMBITS(1) [],
138        KEY1_OUT_0 OFFSET(4) NUMBITS(1) [],
139        KEY2_OUT_0 OFFSET(5) NUMBITS(1) [],
140        Z3_WAKEUP_0 OFFSET(6) NUMBITS(1) [],
141        FLASH_WP_L_0 OFFSET(7) NUMBITS(1) [],
142        BAT_DISABLE_1 OFFSET(8) NUMBITS(1) [],
143        EC_RST_L_1 OFFSET(9) NUMBITS(1) [],
144        PWRB_OUT_1 OFFSET(10) NUMBITS(1) [],
145        KEY0_OUT_1 OFFSET(11) NUMBITS(1) [],
146        KEY1_OUT_1 OFFSET(12) NUMBITS(1) [],
147        KEY2_OUT_1 OFFSET(13) NUMBITS(1) [],
148        Z3_WAKEUP_1 OFFSET(14) NUMBITS(1) [],
149        FLASH_WP_L_1 OFFSET(15) NUMBITS(1) [],
150    ],
151    pub(crate) PIN_OUT_CTL [
152        BAT_DISABLE OFFSET(0) NUMBITS(1) [],
153        EC_RST_L OFFSET(1) NUMBITS(1) [],
154        PWRB_OUT OFFSET(2) NUMBITS(1) [],
155        KEY0_OUT OFFSET(3) NUMBITS(1) [],
156        KEY1_OUT OFFSET(4) NUMBITS(1) [],
157        KEY2_OUT OFFSET(5) NUMBITS(1) [],
158        Z3_WAKEUP OFFSET(6) NUMBITS(1) [],
159        FLASH_WP_L OFFSET(7) NUMBITS(1) [],
160    ],
161    pub(crate) PIN_OUT_VALUE [
162        BAT_DISABLE OFFSET(0) NUMBITS(1) [],
163        EC_RST_L OFFSET(1) NUMBITS(1) [],
164        PWRB_OUT OFFSET(2) NUMBITS(1) [],
165        KEY0_OUT OFFSET(3) NUMBITS(1) [],
166        KEY1_OUT OFFSET(4) NUMBITS(1) [],
167        KEY2_OUT OFFSET(5) NUMBITS(1) [],
168        Z3_WAKEUP OFFSET(6) NUMBITS(1) [],
169        FLASH_WP_L OFFSET(7) NUMBITS(1) [],
170    ],
171    pub(crate) PIN_IN_VALUE [
172        PWRB_IN OFFSET(0) NUMBITS(1) [],
173        KEY0_IN OFFSET(1) NUMBITS(1) [],
174        KEY1_IN OFFSET(2) NUMBITS(1) [],
175        KEY2_IN OFFSET(3) NUMBITS(1) [],
176        LID_OPEN OFFSET(4) NUMBITS(1) [],
177        AC_PRESENT OFFSET(5) NUMBITS(1) [],
178        EC_RST_L OFFSET(6) NUMBITS(1) [],
179        FLASH_WP_L OFFSET(7) NUMBITS(1) [],
180    ],
181    pub(crate) KEY_INTR_CTL [
182        PWRB_IN_H2L OFFSET(0) NUMBITS(1) [],
183        KEY0_IN_H2L OFFSET(1) NUMBITS(1) [],
184        KEY1_IN_H2L OFFSET(2) NUMBITS(1) [],
185        KEY2_IN_H2L OFFSET(3) NUMBITS(1) [],
186        AC_PRESENT_H2L OFFSET(4) NUMBITS(1) [],
187        EC_RST_L_H2L OFFSET(5) NUMBITS(1) [],
188        FLASH_WP_L_H2L OFFSET(6) NUMBITS(1) [],
189        PWRB_IN_L2H OFFSET(7) NUMBITS(1) [],
190        KEY0_IN_L2H OFFSET(8) NUMBITS(1) [],
191        KEY1_IN_L2H OFFSET(9) NUMBITS(1) [],
192        KEY2_IN_L2H OFFSET(10) NUMBITS(1) [],
193        AC_PRESENT_L2H OFFSET(11) NUMBITS(1) [],
194        EC_RST_L_L2H OFFSET(12) NUMBITS(1) [],
195        FLASH_WP_L_L2H OFFSET(13) NUMBITS(1) [],
196    ],
197    pub(crate) KEY_INTR_DEBOUNCE_CTL [
198        DEBOUNCE_TIMER OFFSET(0) NUMBITS(16) [],
199    ],
200    pub(crate) AUTO_BLOCK_DEBOUNCE_CTL [
201        DEBOUNCE_TIMER OFFSET(0) NUMBITS(16) [],
202        AUTO_BLOCK_ENABLE OFFSET(16) NUMBITS(1) [],
203    ],
204    pub(crate) AUTO_BLOCK_OUT_CTL [
205        KEY0_OUT_SEL OFFSET(0) NUMBITS(1) [],
206        KEY1_OUT_SEL OFFSET(1) NUMBITS(1) [],
207        KEY2_OUT_SEL OFFSET(2) NUMBITS(1) [],
208        KEY0_OUT_VALUE OFFSET(4) NUMBITS(1) [],
209        KEY1_OUT_VALUE OFFSET(5) NUMBITS(1) [],
210        KEY2_OUT_VALUE OFFSET(6) NUMBITS(1) [],
211    ],
212    pub(crate) COM_PRE_SEL_CTL [
213        KEY0_IN_SEL_0 OFFSET(0) NUMBITS(1) [],
214        KEY1_IN_SEL_0 OFFSET(1) NUMBITS(1) [],
215        KEY2_IN_SEL_0 OFFSET(2) NUMBITS(1) [],
216        PWRB_IN_SEL_0 OFFSET(3) NUMBITS(1) [],
217        AC_PRESENT_SEL_0 OFFSET(4) NUMBITS(1) [],
218    ],
219    pub(crate) COM_PRE_DET_CTL [
220        PRECONDITION_TIMER_0 OFFSET(0) NUMBITS(32) [],
221    ],
222    pub(crate) COM_SEL_CTL [
223        KEY0_IN_SEL_0 OFFSET(0) NUMBITS(1) [],
224        KEY1_IN_SEL_0 OFFSET(1) NUMBITS(1) [],
225        KEY2_IN_SEL_0 OFFSET(2) NUMBITS(1) [],
226        PWRB_IN_SEL_0 OFFSET(3) NUMBITS(1) [],
227        AC_PRESENT_SEL_0 OFFSET(4) NUMBITS(1) [],
228    ],
229    pub(crate) COM_DET_CTL [
230        DETECTION_TIMER_0 OFFSET(0) NUMBITS(32) [],
231    ],
232    pub(crate) COM_OUT_CTL [
233        BAT_DISABLE_0 OFFSET(0) NUMBITS(1) [],
234        INTERRUPT_0 OFFSET(1) NUMBITS(1) [],
235        EC_RST_0 OFFSET(2) NUMBITS(1) [],
236        RST_REQ_0 OFFSET(3) NUMBITS(1) [],
237    ],
238    pub(crate) COMBO_INTR_STATUS [
239        COMBO0_H2L OFFSET(0) NUMBITS(1) [],
240        COMBO1_H2L OFFSET(1) NUMBITS(1) [],
241        COMBO2_H2L OFFSET(2) NUMBITS(1) [],
242        COMBO3_H2L OFFSET(3) NUMBITS(1) [],
243    ],
244    pub(crate) KEY_INTR_STATUS [
245        PWRB_H2L OFFSET(0) NUMBITS(1) [],
246        KEY0_IN_H2L OFFSET(1) NUMBITS(1) [],
247        KEY1_IN_H2L OFFSET(2) NUMBITS(1) [],
248        KEY2_IN_H2L OFFSET(3) NUMBITS(1) [],
249        AC_PRESENT_H2L OFFSET(4) NUMBITS(1) [],
250        EC_RST_L_H2L OFFSET(5) NUMBITS(1) [],
251        FLASH_WP_L_H2L OFFSET(6) NUMBITS(1) [],
252        PWRB_L2H OFFSET(7) NUMBITS(1) [],
253        KEY0_IN_L2H OFFSET(8) NUMBITS(1) [],
254        KEY1_IN_L2H OFFSET(9) NUMBITS(1) [],
255        KEY2_IN_L2H OFFSET(10) NUMBITS(1) [],
256        AC_PRESENT_L2H OFFSET(11) NUMBITS(1) [],
257        EC_RST_L_L2H OFFSET(12) NUMBITS(1) [],
258        FLASH_WP_L_L2H OFFSET(13) NUMBITS(1) [],
259    ],
260];
261
262// End generated register constants for sysrst_ctrl
lowrisc/registers/sysrst_ctrl_regs.rs

lowrisc/registers/
sysrst_ctrl_regs.rs
