lowrisc/registers/
otp_ctrl_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for otp_ctrl.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/otp_ctrl/data/otp_ctrl.hjson
12use kernel::utilities::registers::ReadOnly;
13use kernel::utilities::registers::ReadWrite;
14use kernel::utilities::registers::{register_bitfields, register_structs};
15/// Number of key slots
16pub const OTP_CTRL_PARAM_NUM_SRAM_KEY_REQ_SLOTS: u32 = 3;
17/// Width of the OTP byte address.
18pub const OTP_CTRL_PARAM_OTP_BYTE_ADDR_WIDTH: u32 = 11;
19/// Number of error register entries.
20pub const OTP_CTRL_PARAM_NUM_ERROR_ENTRIES: u32 = 10;
21/// Number of 32bit words in the DAI.
22pub const OTP_CTRL_PARAM_NUM_DAI_WORDS: u32 = 2;
23/// Size of the digest fields in 32bit words.
24pub const OTP_CTRL_PARAM_NUM_DIGEST_WORDS: u32 = 2;
25/// Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller
26/// than that.
27pub const OTP_CTRL_PARAM_NUM_SW_CFG_WINDOW_WORDS: u32 = 512;
28/// Number of partitions
29pub const OTP_CTRL_PARAM_NUM_PART: u32 = 8;
30/// Offset of the VENDOR_TEST partition
31pub const OTP_CTRL_PARAM_VENDOR_TEST_OFFSET: usize = 0;
32/// Size of the VENDOR_TEST partition
33pub const OTP_CTRL_PARAM_VENDOR_TEST_SIZE: u32 = 64;
34/// Offset of SCRATCH
35pub const OTP_CTRL_PARAM_SCRATCH_OFFSET: usize = 0;
36/// Size of SCRATCH
37pub const OTP_CTRL_PARAM_SCRATCH_SIZE: u32 = 56;
38/// Offset of VENDOR_TEST_DIGEST
39pub const OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_OFFSET: usize = 56;
40/// Size of VENDOR_TEST_DIGEST
41pub const OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_SIZE: u32 = 8;
42/// Offset of the CREATOR_SW_CFG partition
43pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_OFFSET: usize = 64;
44/// Size of the CREATOR_SW_CFG partition
45pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIZE: u32 = 800;
46/// Offset of CREATOR_SW_CFG_AST_CFG
47pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_OFFSET: usize = 64;
48/// Size of CREATOR_SW_CFG_AST_CFG
49pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_SIZE: u32 = 156;
50/// Offset of CREATOR_SW_CFG_AST_INIT_EN
51pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_OFFSET: usize = 220;
52/// Size of CREATOR_SW_CFG_AST_INIT_EN
53pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_INIT_EN_SIZE: u32 = 4;
54/// Offset of CREATOR_SW_CFG_ROM_EXT_SKU
55pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_OFFSET: usize = 224;
56/// Size of CREATOR_SW_CFG_ROM_EXT_SKU
57pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXT_SKU_SIZE: u32 = 4;
58/// Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN
59pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_OFFSET: usize = 228;
60/// Size of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN
61pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_SIZE: u32 = 4;
62/// Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN
63pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_OFFSET: usize = 232;
64/// Size of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN
65pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_SIZE: u32 = 8;
66/// Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_EN
67pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_OFFSET: usize = 240;
68/// Size of CREATOR_SW_CFG_SIGVERIFY_SPX_EN
69pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_EN_SIZE: u32 = 4;
70/// Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN
71pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_OFFSET: usize = 244;
72/// Size of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN
73pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_SIZE: u32 = 8;
74/// Offset of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG
75pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_OFFSET: usize = 252;
76/// Size of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG
77pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_SIZE: u32 = 4;
78/// Offset of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG
79pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_OFFSET: usize = 256;
80/// Size of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG
81pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_SIZE: u32 = 4;
82/// Offset of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE
83pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_OFFSET: usize = 260;
84/// Size of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE
85pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_SIZE: u32 = 4;
86/// Offset of CREATOR_SW_CFG_RNG_EN
87pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_OFFSET: usize = 264;
88/// Size of CREATOR_SW_CFG_RNG_EN
89pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EN_SIZE: u32 = 4;
90/// Offset of CREATOR_SW_CFG_JITTER_EN
91pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_OFFSET: usize = 268;
92/// Size of CREATOR_SW_CFG_JITTER_EN
93pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_JITTER_EN_SIZE: u32 = 4;
94/// Offset of CREATOR_SW_CFG_RET_RAM_RESET_MASK
95pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_OFFSET: usize = 272;
96/// Size of CREATOR_SW_CFG_RET_RAM_RESET_MASK
97pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RET_RAM_RESET_MASK_SIZE: u32 = 4;
98/// Offset of CREATOR_SW_CFG_MANUF_STATE
99pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_OFFSET: usize = 276;
100/// Size of CREATOR_SW_CFG_MANUF_STATE
101pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_MANUF_STATE_SIZE: u32 = 4;
102/// Offset of CREATOR_SW_CFG_ROM_EXEC_EN
103pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_OFFSET: usize = 280;
104/// Size of CREATOR_SW_CFG_ROM_EXEC_EN
105pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_ROM_EXEC_EN_SIZE: u32 = 4;
106/// Offset of CREATOR_SW_CFG_CPUCTRL
107pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_OFFSET: usize = 284;
108/// Size of CREATOR_SW_CFG_CPUCTRL
109pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_CPUCTRL_SIZE: u32 = 4;
110/// Offset of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT
111pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_OFFSET: usize = 288;
112/// Size of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT
113pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_SIZE: u32 = 4;
114/// Offset of CREATOR_SW_CFG_MIN_SEC_VER_BL0
115pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_OFFSET: usize = 292;
116/// Size of CREATOR_SW_CFG_MIN_SEC_VER_BL0
117pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_MIN_SEC_VER_BL0_SIZE: u32 = 4;
118/// Offset of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN
119pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_OFFSET: usize = 296;
120/// Size of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN
121pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_SIZE: u32 = 4;
122/// Offset of CREATOR_SW_CFG_RMA_SPIN_EN
123pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_OFFSET: usize = 300;
124/// Size of CREATOR_SW_CFG_RMA_SPIN_EN
125pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_EN_SIZE: u32 = 4;
126/// Offset of CREATOR_SW_CFG_RMA_SPIN_CYCLES
127pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_OFFSET: usize = 304;
128/// Size of CREATOR_SW_CFG_RMA_SPIN_CYCLES
129pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RMA_SPIN_CYCLES_SIZE: u32 = 4;
130/// Offset of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS
131pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_OFFSET: usize = 308;
132/// Size of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS
133pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_SIZE: u32 = 4;
134/// Offset of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS
135pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_OFFSET: usize = 312;
136/// Size of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS
137pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_SIZE: u32 = 4;
138/// Offset of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS
139pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_OFFSET: usize = 316;
140/// Size of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS
141pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_SIZE: u32 = 4;
142/// Offset of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS
143pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_OFFSET: usize = 320;
144/// Size of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS
145pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_SIZE: u32 = 4;
146/// Offset of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS
147pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_OFFSET: usize = 324;
148/// Size of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS
149pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_SIZE: u32 = 4;
150/// Offset of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS
151pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_OFFSET: usize = 328;
152/// Size of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS
153pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_SIZE: u32 = 4;
154/// Offset of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS
155pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_OFFSET: usize = 332;
156/// Size of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS
157pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_SIZE: u32 = 4;
158/// Offset of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS
159pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_OFFSET: usize = 336;
160/// Size of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS
161pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_SIZE: u32 = 4;
162/// Offset of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS
163pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_OFFSET: usize = 340;
164/// Size of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS
165pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_SIZE: u32 = 4;
166/// Offset of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD
167pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_OFFSET: usize = 344;
168/// Size of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD
169pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_SIZE: u32 = 4;
170/// Offset of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST
171pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_OFFSET: usize = 348;
172/// Size of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST
173pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_SIZE: u32 = 4;
174/// Offset of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN
175pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_OFFSET: usize = 352;
176/// Size of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN
177pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_SIZE: u32 = 4;
178/// Offset of CREATOR_SW_CFG_DIGEST
179pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_OFFSET: usize = 856;
180/// Size of CREATOR_SW_CFG_DIGEST
181pub const OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_SIZE: u32 = 8;
182/// Offset of the OWNER_SW_CFG partition
183pub const OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET: usize = 864;
184/// Size of the OWNER_SW_CFG partition
185pub const OTP_CTRL_PARAM_OWNER_SW_CFG_SIZE: u32 = 800;
186/// Offset of OWNER_SW_CFG_ROM_ERROR_REPORTING
187pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_OFFSET: usize = 864;
188/// Size of OWNER_SW_CFG_ROM_ERROR_REPORTING
189pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ERROR_REPORTING_SIZE: u32 = 4;
190/// Offset of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS
191pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_OFFSET: usize = 868;
192/// Size of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS
193pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_SIZE: u32 = 4;
194/// Offset of OWNER_SW_CFG_ROM_ALERT_CLASS_EN
195pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_OFFSET: usize = 872;
196/// Size of OWNER_SW_CFG_ROM_ALERT_CLASS_EN
197pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASS_EN_SIZE: u32 = 4;
198/// Offset of OWNER_SW_CFG_ROM_ALERT_ESCALATION
199pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_OFFSET: usize = 876;
200/// Size of OWNER_SW_CFG_ROM_ALERT_ESCALATION
201pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ESCALATION_SIZE: u32 = 4;
202/// Offset of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION
203pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_OFFSET: usize = 880;
204/// Size of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION
205pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE: u32 = 320;
206/// Offset of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION
207pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_OFFSET: usize = 1200;
208/// Size of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION
209pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE: u32 = 64;
210/// Offset of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH
211pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_OFFSET: usize = 1264;
212/// Size of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH
213pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_SIZE: u32 = 16;
214/// Offset of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES
215pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_OFFSET: usize = 1280;
216/// Size of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES
217pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE: u32 = 16;
218/// Offset of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES
219pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_OFFSET: usize = 1296;
220/// Size of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES
221pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE: u32 = 64;
222/// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD
223pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_OFFSET: usize = 1360;
224/// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD
225pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_SIZE: u32 = 4;
226/// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END
227pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_OFFSET: usize = 1364;
228/// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END
229pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_SIZE: u32 = 4;
230/// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV
231pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_OFFSET: usize = 1368;
232/// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV
233pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_SIZE: u32 = 4;
234/// Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA
235pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_OFFSET: usize = 1372;
236/// Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA
237pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_SIZE: u32 = 4;
238/// Offset of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES
239pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_OFFSET: usize = 1376;
240/// Size of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES
241pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_SIZE: u32 = 4;
242/// Offset of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN
243pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_OFFSET: usize = 1380;
244/// Size of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN
245pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_SIZE: u32 = 4;
246/// Offset of OWNER_SW_CFG_MANUF_STATE
247pub const OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_OFFSET: usize = 1384;
248/// Size of OWNER_SW_CFG_MANUF_STATE
249pub const OTP_CTRL_PARAM_OWNER_SW_CFG_MANUF_STATE_SIZE: u32 = 4;
250/// Offset of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN
251pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_OFFSET: usize = 1388;
252/// Size of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN
253pub const OTP_CTRL_PARAM_OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_SIZE: u32 = 4;
254/// Offset of OWNER_SW_CFG_DIGEST
255pub const OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_OFFSET: usize = 1656;
256/// Size of OWNER_SW_CFG_DIGEST
257pub const OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_SIZE: u32 = 8;
258/// Offset of the HW_CFG partition
259pub const OTP_CTRL_PARAM_HW_CFG_OFFSET: usize = 1664;
260/// Size of the HW_CFG partition
261pub const OTP_CTRL_PARAM_HW_CFG_SIZE: u32 = 80;
262/// Offset of DEVICE_ID
263pub const OTP_CTRL_PARAM_DEVICE_ID_OFFSET: usize = 1664;
264/// Size of DEVICE_ID
265pub const OTP_CTRL_PARAM_DEVICE_ID_SIZE: u32 = 32;
266/// Offset of MANUF_STATE
267pub const OTP_CTRL_PARAM_MANUF_STATE_OFFSET: usize = 1696;
268/// Size of MANUF_STATE
269pub const OTP_CTRL_PARAM_MANUF_STATE_SIZE: u32 = 32;
270/// Offset of EN_SRAM_IFETCH
271pub const OTP_CTRL_PARAM_EN_SRAM_IFETCH_OFFSET: usize = 1728;
272/// Size of EN_SRAM_IFETCH
273pub const OTP_CTRL_PARAM_EN_SRAM_IFETCH_SIZE: u32 = 1;
274/// Offset of EN_CSRNG_SW_APP_READ
275pub const OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_OFFSET: usize = 1729;
276/// Size of EN_CSRNG_SW_APP_READ
277pub const OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_SIZE: u32 = 1;
278/// Offset of EN_ENTROPY_SRC_FW_READ
279pub const OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_READ_OFFSET: usize = 1730;
280/// Size of EN_ENTROPY_SRC_FW_READ
281pub const OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_READ_SIZE: u32 = 1;
282/// Offset of EN_ENTROPY_SRC_FW_OVER
283pub const OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_OVER_OFFSET: usize = 1731;
284/// Size of EN_ENTROPY_SRC_FW_OVER
285pub const OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_OVER_SIZE: u32 = 1;
286/// Offset of HW_CFG_DIGEST
287pub const OTP_CTRL_PARAM_HW_CFG_DIGEST_OFFSET: usize = 1736;
288/// Size of HW_CFG_DIGEST
289pub const OTP_CTRL_PARAM_HW_CFG_DIGEST_SIZE: u32 = 8;
290/// Offset of the SECRET0 partition
291pub const OTP_CTRL_PARAM_SECRET0_OFFSET: usize = 1744;
292/// Size of the SECRET0 partition
293pub const OTP_CTRL_PARAM_SECRET0_SIZE: u32 = 40;
294/// Offset of TEST_UNLOCK_TOKEN
295pub const OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_OFFSET: usize = 1744;
296/// Size of TEST_UNLOCK_TOKEN
297pub const OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_SIZE: u32 = 16;
298/// Offset of TEST_EXIT_TOKEN
299pub const OTP_CTRL_PARAM_TEST_EXIT_TOKEN_OFFSET: usize = 1760;
300/// Size of TEST_EXIT_TOKEN
301pub const OTP_CTRL_PARAM_TEST_EXIT_TOKEN_SIZE: u32 = 16;
302/// Offset of SECRET0_DIGEST
303pub const OTP_CTRL_PARAM_SECRET0_DIGEST_OFFSET: usize = 1776;
304/// Size of SECRET0_DIGEST
305pub const OTP_CTRL_PARAM_SECRET0_DIGEST_SIZE: u32 = 8;
306/// Offset of the SECRET1 partition
307pub const OTP_CTRL_PARAM_SECRET1_OFFSET: usize = 1784;
308/// Size of the SECRET1 partition
309pub const OTP_CTRL_PARAM_SECRET1_SIZE: u32 = 88;
310/// Offset of FLASH_ADDR_KEY_SEED
311pub const OTP_CTRL_PARAM_FLASH_ADDR_KEY_SEED_OFFSET: usize = 1784;
312/// Size of FLASH_ADDR_KEY_SEED
313pub const OTP_CTRL_PARAM_FLASH_ADDR_KEY_SEED_SIZE: u32 = 32;
314/// Offset of FLASH_DATA_KEY_SEED
315pub const OTP_CTRL_PARAM_FLASH_DATA_KEY_SEED_OFFSET: usize = 1816;
316/// Size of FLASH_DATA_KEY_SEED
317pub const OTP_CTRL_PARAM_FLASH_DATA_KEY_SEED_SIZE: u32 = 32;
318/// Offset of SRAM_DATA_KEY_SEED
319pub const OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_OFFSET: usize = 1848;
320/// Size of SRAM_DATA_KEY_SEED
321pub const OTP_CTRL_PARAM_SRAM_DATA_KEY_SEED_SIZE: u32 = 16;
322/// Offset of SECRET1_DIGEST
323pub const OTP_CTRL_PARAM_SECRET1_DIGEST_OFFSET: usize = 1864;
324/// Size of SECRET1_DIGEST
325pub const OTP_CTRL_PARAM_SECRET1_DIGEST_SIZE: u32 = 8;
326/// Offset of the SECRET2 partition
327pub const OTP_CTRL_PARAM_SECRET2_OFFSET: usize = 1872;
328/// Size of the SECRET2 partition
329pub const OTP_CTRL_PARAM_SECRET2_SIZE: u32 = 88;
330/// Offset of RMA_TOKEN
331pub const OTP_CTRL_PARAM_RMA_TOKEN_OFFSET: usize = 1872;
332/// Size of RMA_TOKEN
333pub const OTP_CTRL_PARAM_RMA_TOKEN_SIZE: u32 = 16;
334/// Offset of CREATOR_ROOT_KEY_SHARE0
335pub const OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_OFFSET: usize = 1888;
336/// Size of CREATOR_ROOT_KEY_SHARE0
337pub const OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE0_SIZE: u32 = 32;
338/// Offset of CREATOR_ROOT_KEY_SHARE1
339pub const OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_OFFSET: usize = 1920;
340/// Size of CREATOR_ROOT_KEY_SHARE1
341pub const OTP_CTRL_PARAM_CREATOR_ROOT_KEY_SHARE1_SIZE: u32 = 32;
342/// Offset of SECRET2_DIGEST
343pub const OTP_CTRL_PARAM_SECRET2_DIGEST_OFFSET: usize = 1952;
344/// Size of SECRET2_DIGEST
345pub const OTP_CTRL_PARAM_SECRET2_DIGEST_SIZE: u32 = 8;
346/// Offset of the LIFE_CYCLE partition
347pub const OTP_CTRL_PARAM_LIFE_CYCLE_OFFSET: usize = 1960;
348/// Size of the LIFE_CYCLE partition
349pub const OTP_CTRL_PARAM_LIFE_CYCLE_SIZE: u32 = 88;
350/// Offset of LC_TRANSITION_CNT
351pub const OTP_CTRL_PARAM_LC_TRANSITION_CNT_OFFSET: usize = 1960;
352/// Size of LC_TRANSITION_CNT
353pub const OTP_CTRL_PARAM_LC_TRANSITION_CNT_SIZE: u32 = 48;
354/// Offset of LC_STATE
355pub const OTP_CTRL_PARAM_LC_STATE_OFFSET: usize = 2008;
356/// Size of LC_STATE
357pub const OTP_CTRL_PARAM_LC_STATE_SIZE: u32 = 40;
358/// Number of alerts
359pub const OTP_CTRL_PARAM_NUM_ALERTS: u32 = 5;
360/// Register width
361pub const OTP_CTRL_PARAM_REG_WIDTH: u32 = 32;
362
363register_structs! {
364    pub OtpCtrlRegisters {
365        /// Interrupt State Register
366        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
367        /// Interrupt Enable Register
368        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
369        /// Interrupt Test Register
370        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
371        /// Alert Test Register
372        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
373        /// OTP status register.
374        (0x0010 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
375        /// This register holds information about error conditions that occurred in the agents
376        (0x0014 => pub(crate) err_code: [ReadWrite<u32, ERR_CODE::Register>; 1]),
377        /// Register write enable for all direct access interface registers.
378        (0x0018 => pub(crate) direct_access_regwen: ReadWrite<u32, DIRECT_ACCESS_REGWEN::Register>),
379        /// Command register for direct accesses.
380        (0x001c => pub(crate) direct_access_cmd: ReadWrite<u32, DIRECT_ACCESS_CMD::Register>),
381        /// Address register for direct accesses.
382        (0x0020 => pub(crate) direct_access_address: ReadWrite<u32, DIRECT_ACCESS_ADDRESS::Register>),
383        /// Write data for direct accesses.
384        (0x0024 => pub(crate) direct_access_wdata: [ReadWrite<u32, DIRECT_ACCESS_WDATA::Register>; 2]),
385        /// Read data for direct accesses.
386        (0x002c => pub(crate) direct_access_rdata: [ReadWrite<u32, DIRECT_ACCESS_RDATA::Register>; 2]),
387        /// Register write enable for !!CHECK_TRIGGER.
388        (0x0034 => pub(crate) check_trigger_regwen: ReadWrite<u32, CHECK_TRIGGER_REGWEN::Register>),
389        /// Command register for direct accesses.
390        (0x0038 => pub(crate) check_trigger: ReadWrite<u32, CHECK_TRIGGER::Register>),
391        /// Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD.
392        (0x003c => pub(crate) check_regwen: ReadWrite<u32, CHECK_REGWEN::Register>),
393        /// Timeout value for the integrity and consistency checks.
394        (0x0040 => pub(crate) check_timeout: ReadWrite<u32, CHECK_TIMEOUT::Register>),
395        /// This value specifies the maximum period that can be generated pseudo-randomly.
396        (0x0044 => pub(crate) integrity_check_period: ReadWrite<u32, INTEGRITY_CHECK_PERIOD::Register>),
397        /// This value specifies the maximum period that can be generated pseudo-randomly.
398        (0x0048 => pub(crate) consistency_check_period: ReadWrite<u32, CONSISTENCY_CHECK_PERIOD::Register>),
399        /// Runtime read lock for the VENDOR_TEST partition.
400        (0x004c => pub(crate) vendor_test_read_lock: ReadWrite<u32, VENDOR_TEST_READ_LOCK::Register>),
401        /// Runtime read lock for the CREATOR_SW_CFG partition.
402        (0x0050 => pub(crate) creator_sw_cfg_read_lock: ReadWrite<u32, CREATOR_SW_CFG_READ_LOCK::Register>),
403        /// Runtime read lock for the OWNER_SW_CFG partition.
404        (0x0054 => pub(crate) owner_sw_cfg_read_lock: ReadWrite<u32, OWNER_SW_CFG_READ_LOCK::Register>),
405        /// Integrity digest for the VENDOR_TEST partition.
406        (0x0058 => pub(crate) vendor_test_digest: [ReadWrite<u32, VENDOR_TEST_DIGEST::Register>; 2]),
407        /// Integrity digest for the CREATOR_SW_CFG partition.
408        (0x0060 => pub(crate) creator_sw_cfg_digest: [ReadWrite<u32, CREATOR_SW_CFG_DIGEST::Register>; 2]),
409        /// Integrity digest for the OWNER_SW_CFG partition.
410        (0x0068 => pub(crate) owner_sw_cfg_digest: [ReadWrite<u32, OWNER_SW_CFG_DIGEST::Register>; 2]),
411        /// Integrity digest for the HW_CFG partition.
412        (0x0070 => pub(crate) hw_cfg_digest: [ReadWrite<u32, HW_CFG_DIGEST::Register>; 2]),
413        /// Integrity digest for the SECRET0 partition.
414        (0x0078 => pub(crate) secret0_digest: [ReadWrite<u32, SECRET0_DIGEST::Register>; 2]),
415        /// Integrity digest for the SECRET1 partition.
416        (0x0080 => pub(crate) secret1_digest: [ReadWrite<u32, SECRET1_DIGEST::Register>; 2]),
417        /// Integrity digest for the SECRET2 partition.
418        (0x0088 => pub(crate) secret2_digest: [ReadWrite<u32, SECRET2_DIGEST::Register>; 2]),
419        (0x0090 => _reserved1),
420        /// Memory area: Any read to this window directly maps to the corresponding offset in the creator
421        /// and owner software
422        (0x1000 => pub(crate) sw_cfg_window: [ReadOnly<u32>; 512]),
423        (0x1800 => @END),
424    }
425}
426
427register_bitfields![u32,
428    /// Common Interrupt Offsets
429    pub(crate) INTR [
430        OTP_OPERATION_DONE OFFSET(0) NUMBITS(1) [],
431        OTP_ERROR OFFSET(1) NUMBITS(1) [],
432    ],
433    pub(crate) ALERT_TEST [
434        FATAL_MACRO_ERROR OFFSET(0) NUMBITS(1) [],
435        FATAL_CHECK_ERROR OFFSET(1) NUMBITS(1) [],
436        FATAL_BUS_INTEG_ERROR OFFSET(2) NUMBITS(1) [],
437        FATAL_PRIM_OTP_ALERT OFFSET(3) NUMBITS(1) [],
438        RECOV_PRIM_OTP_ALERT OFFSET(4) NUMBITS(1) [],
439    ],
440    pub(crate) STATUS [
441        VENDOR_TEST_ERROR OFFSET(0) NUMBITS(1) [],
442        CREATOR_SW_CFG_ERROR OFFSET(1) NUMBITS(1) [],
443        OWNER_SW_CFG_ERROR OFFSET(2) NUMBITS(1) [],
444        HW_CFG_ERROR OFFSET(3) NUMBITS(1) [],
445        SECRET0_ERROR OFFSET(4) NUMBITS(1) [],
446        SECRET1_ERROR OFFSET(5) NUMBITS(1) [],
447        SECRET2_ERROR OFFSET(6) NUMBITS(1) [],
448        LIFE_CYCLE_ERROR OFFSET(7) NUMBITS(1) [],
449        DAI_ERROR OFFSET(8) NUMBITS(1) [],
450        LCI_ERROR OFFSET(9) NUMBITS(1) [],
451        TIMEOUT_ERROR OFFSET(10) NUMBITS(1) [],
452        LFSR_FSM_ERROR OFFSET(11) NUMBITS(1) [],
453        SCRAMBLING_FSM_ERROR OFFSET(12) NUMBITS(1) [],
454        KEY_DERIV_FSM_ERROR OFFSET(13) NUMBITS(1) [],
455        BUS_INTEG_ERROR OFFSET(14) NUMBITS(1) [],
456        DAI_IDLE OFFSET(15) NUMBITS(1) [],
457        CHECK_PENDING OFFSET(16) NUMBITS(1) [],
458    ],
459    pub(crate) ERR_CODE [
460        ERR_CODE_0 OFFSET(0) NUMBITS(3) [
461            NO_ERROR = 0,
462            MACRO_ERROR = 1,
463            MACRO_ECC_CORR_ERROR = 2,
464            MACRO_ECC_UNCORR_ERROR = 3,
465            MACRO_WRITE_BLANK_ERROR = 4,
466            ACCESS_ERROR = 5,
467            CHECK_FAIL_ERROR = 6,
468            FSM_STATE_ERROR = 7,
469        ],
470        ERR_CODE_1 OFFSET(3) NUMBITS(3) [
471            NO_ERROR = 0,
472            MACRO_ERROR = 1,
473            MACRO_ECC_CORR_ERROR = 2,
474            MACRO_ECC_UNCORR_ERROR = 3,
475            MACRO_WRITE_BLANK_ERROR = 4,
476            ACCESS_ERROR = 5,
477            CHECK_FAIL_ERROR = 6,
478            FSM_STATE_ERROR = 7,
479        ],
480        ERR_CODE_2 OFFSET(6) NUMBITS(3) [
481            NO_ERROR = 0,
482            MACRO_ERROR = 1,
483            MACRO_ECC_CORR_ERROR = 2,
484            MACRO_ECC_UNCORR_ERROR = 3,
485            MACRO_WRITE_BLANK_ERROR = 4,
486            ACCESS_ERROR = 5,
487            CHECK_FAIL_ERROR = 6,
488            FSM_STATE_ERROR = 7,
489        ],
490        ERR_CODE_3 OFFSET(9) NUMBITS(3) [
491            NO_ERROR = 0,
492            MACRO_ERROR = 1,
493            MACRO_ECC_CORR_ERROR = 2,
494            MACRO_ECC_UNCORR_ERROR = 3,
495            MACRO_WRITE_BLANK_ERROR = 4,
496            ACCESS_ERROR = 5,
497            CHECK_FAIL_ERROR = 6,
498            FSM_STATE_ERROR = 7,
499        ],
500        ERR_CODE_4 OFFSET(12) NUMBITS(3) [
501            NO_ERROR = 0,
502            MACRO_ERROR = 1,
503            MACRO_ECC_CORR_ERROR = 2,
504            MACRO_ECC_UNCORR_ERROR = 3,
505            MACRO_WRITE_BLANK_ERROR = 4,
506            ACCESS_ERROR = 5,
507            CHECK_FAIL_ERROR = 6,
508            FSM_STATE_ERROR = 7,
509        ],
510        ERR_CODE_5 OFFSET(15) NUMBITS(3) [
511            NO_ERROR = 0,
512            MACRO_ERROR = 1,
513            MACRO_ECC_CORR_ERROR = 2,
514            MACRO_ECC_UNCORR_ERROR = 3,
515            MACRO_WRITE_BLANK_ERROR = 4,
516            ACCESS_ERROR = 5,
517            CHECK_FAIL_ERROR = 6,
518            FSM_STATE_ERROR = 7,
519        ],
520        ERR_CODE_6 OFFSET(18) NUMBITS(3) [
521            NO_ERROR = 0,
522            MACRO_ERROR = 1,
523            MACRO_ECC_CORR_ERROR = 2,
524            MACRO_ECC_UNCORR_ERROR = 3,
525            MACRO_WRITE_BLANK_ERROR = 4,
526            ACCESS_ERROR = 5,
527            CHECK_FAIL_ERROR = 6,
528            FSM_STATE_ERROR = 7,
529        ],
530        ERR_CODE_7 OFFSET(21) NUMBITS(3) [
531            NO_ERROR = 0,
532            MACRO_ERROR = 1,
533            MACRO_ECC_CORR_ERROR = 2,
534            MACRO_ECC_UNCORR_ERROR = 3,
535            MACRO_WRITE_BLANK_ERROR = 4,
536            ACCESS_ERROR = 5,
537            CHECK_FAIL_ERROR = 6,
538            FSM_STATE_ERROR = 7,
539        ],
540        ERR_CODE_8 OFFSET(24) NUMBITS(3) [
541            NO_ERROR = 0,
542            MACRO_ERROR = 1,
543            MACRO_ECC_CORR_ERROR = 2,
544            MACRO_ECC_UNCORR_ERROR = 3,
545            MACRO_WRITE_BLANK_ERROR = 4,
546            ACCESS_ERROR = 5,
547            CHECK_FAIL_ERROR = 6,
548            FSM_STATE_ERROR = 7,
549        ],
550        ERR_CODE_9 OFFSET(27) NUMBITS(3) [
551            NO_ERROR = 0,
552            MACRO_ERROR = 1,
553            MACRO_ECC_CORR_ERROR = 2,
554            MACRO_ECC_UNCORR_ERROR = 3,
555            MACRO_WRITE_BLANK_ERROR = 4,
556            ACCESS_ERROR = 5,
557            CHECK_FAIL_ERROR = 6,
558            FSM_STATE_ERROR = 7,
559        ],
560    ],
561    pub(crate) DIRECT_ACCESS_REGWEN [
562        DIRECT_ACCESS_REGWEN OFFSET(0) NUMBITS(1) [],
563    ],
564    pub(crate) DIRECT_ACCESS_CMD [
565        RD OFFSET(0) NUMBITS(1) [],
566        WR OFFSET(1) NUMBITS(1) [],
567        DIGEST OFFSET(2) NUMBITS(1) [],
568    ],
569    pub(crate) DIRECT_ACCESS_ADDRESS [
570        DIRECT_ACCESS_ADDRESS OFFSET(0) NUMBITS(11) [],
571    ],
572    pub(crate) DIRECT_ACCESS_WDATA [
573        DIRECT_ACCESS_WDATA_0 OFFSET(0) NUMBITS(32) [],
574    ],
575    pub(crate) DIRECT_ACCESS_RDATA [
576        DIRECT_ACCESS_RDATA_0 OFFSET(0) NUMBITS(32) [],
577    ],
578    pub(crate) CHECK_TRIGGER_REGWEN [
579        CHECK_TRIGGER_REGWEN OFFSET(0) NUMBITS(1) [],
580    ],
581    pub(crate) CHECK_TRIGGER [
582        INTEGRITY OFFSET(0) NUMBITS(1) [],
583        CONSISTENCY OFFSET(1) NUMBITS(1) [],
584    ],
585    pub(crate) CHECK_REGWEN [
586        CHECK_REGWEN OFFSET(0) NUMBITS(1) [],
587    ],
588    pub(crate) CHECK_TIMEOUT [
589        CHECK_TIMEOUT OFFSET(0) NUMBITS(32) [],
590    ],
591    pub(crate) INTEGRITY_CHECK_PERIOD [
592        INTEGRITY_CHECK_PERIOD OFFSET(0) NUMBITS(32) [],
593    ],
594    pub(crate) CONSISTENCY_CHECK_PERIOD [
595        CONSISTENCY_CHECK_PERIOD OFFSET(0) NUMBITS(32) [],
596    ],
597    pub(crate) VENDOR_TEST_READ_LOCK [
598        VENDOR_TEST_READ_LOCK OFFSET(0) NUMBITS(1) [],
599    ],
600    pub(crate) CREATOR_SW_CFG_READ_LOCK [
601        CREATOR_SW_CFG_READ_LOCK OFFSET(0) NUMBITS(1) [],
602    ],
603    pub(crate) OWNER_SW_CFG_READ_LOCK [
604        OWNER_SW_CFG_READ_LOCK OFFSET(0) NUMBITS(1) [],
605    ],
606    pub(crate) VENDOR_TEST_DIGEST [
607        VENDOR_TEST_DIGEST_0 OFFSET(0) NUMBITS(32) [],
608    ],
609    pub(crate) CREATOR_SW_CFG_DIGEST [
610        CREATOR_SW_CFG_DIGEST_0 OFFSET(0) NUMBITS(32) [],
611    ],
612    pub(crate) OWNER_SW_CFG_DIGEST [
613        OWNER_SW_CFG_DIGEST_0 OFFSET(0) NUMBITS(32) [],
614    ],
615    pub(crate) HW_CFG_DIGEST [
616        HW_CFG_DIGEST_0 OFFSET(0) NUMBITS(32) [],
617    ],
618    pub(crate) SECRET0_DIGEST [
619        SECRET0_DIGEST_0 OFFSET(0) NUMBITS(32) [],
620    ],
621    pub(crate) SECRET1_DIGEST [
622        SECRET1_DIGEST_0 OFFSET(0) NUMBITS(32) [],
623    ],
624    pub(crate) SECRET2_DIGEST [
625        SECRET2_DIGEST_0 OFFSET(0) NUMBITS(32) [],
626    ],
627];
628
629// End generated register constants for otp_ctrl
lowrisc/registers/otp_ctrl_regs.rs

lowrisc/registers/
otp_ctrl_regs.rs
