nrf52/
ppi.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Programmable peripheral interconnect, nRF52
6//!
7//! Chapter 20 of the nRF52832 Objective Product Specification v0.6.3:
8//!
9//! The PPI provides a mechanism to automatically trigger a task in one peripheral
10//! as a result of an event occurring in another peripheral. A task is connected to
11//! an event through a PPI channel.
12//! The PPI channel is composed of three end point registers, one event end point (EEP)
13//! and two task end points (TEP).
14//! A peripheral task is connected to a TEP using the address of the task register
15//! associated with the task. Similarly, a peripheral event is connected to an EEP using
16//! the address of the event register associated with the event.
17//!
18//! Pre-programmed Channels
19//! (Channel EEP TEP):
20//!
21//! * 20        `TIMER0->EVENTS_COMPARE[0]`       `RADIO->TASKS_TXEN`
22//! * 21        `TIMER0->EVENTS_COMPARE[0]`       `RADIO->TASKS_RXEN`
23//! * 22        `TIMER0->EVENTS_COMPARE[1]`       `RADIO->TASKS_DISABLE`
24//! * 23        `RADIO->EVENTS_BCMATCH`           `AAR->TASKS_START`
25//! * 24        `RADIO->EVENTS_READY`             `CCM->TASKS_KSGEN`
26//! * 25        `RADIO->EVENTS_ADDRESS`           `CCM->TASKS_CRYPT`
27//! * 26        `RADIO->EVENTS_ADDRESS`           `TIMER0->TASKS_CAPTURE[1]`
28//! * 27        `RADIO->EVENTS_END`               `TIMER0->TASKS_CAPTURE[2]`
29//! * 28        `RTC0->EVENTS_COMPARE[0]`         `RADIO->TASKS_TXEN`
30//! * 29        `RTC0->EVENTS_COMPARE[0]`         `RADIO->TASKS_RXEN`
31//! * 30        `RTC0->EVENTS_COMPARE[0]`         `TIMER0->TASKS_CLEAR`
32//! * 31        `RTC0->EVENTS_COMPARE[0]`         `TIMER0->TASKS_START`
33//!
34//! Authors
35//! ---------
36//! * Johan Lindskogen
37//! * Francine Mäkelä
38//! * Date: May 04, 2018
39
40use kernel::utilities::registers::interfaces::Writeable;
41use kernel::utilities::registers::{register_bitfields, FieldValue, ReadWrite};
42use kernel::utilities::StaticRef;
43
44const PPI_BASE: StaticRef<PpiRegisters> =
45    unsafe { StaticRef::new(0x4001F000 as *const PpiRegisters) };
46
47#[repr(C)]
48struct PpiRegisters {
49    tasks_chg0_en: ReadWrite<u32, Control::Register>,
50    tasks_chg0_dis: ReadWrite<u32, Control::Register>,
51    tasks_chg1_en: ReadWrite<u32, Control::Register>,
52    tasks_chg1_dis: ReadWrite<u32, Control::Register>,
53    tasks_chg2_en: ReadWrite<u32, Control::Register>,
54    tasks_chg2_dis: ReadWrite<u32, Control::Register>,
55    tasks_chg3_en: ReadWrite<u32, Control::Register>,
56    tasks_chg3_dis: ReadWrite<u32, Control::Register>,
57    tasks_chg4_en: ReadWrite<u32, Control::Register>,
58    tasks_chg4_dis: ReadWrite<u32, Control::Register>,
59    tasks_chg5_en: ReadWrite<u32, Control::Register>,
60    tasks_chg5_dis: ReadWrite<u32, Control::Register>,
61    _reserved1: [u32; 308],
62    chen: ReadWrite<u32, Channel::Register>,
63    chenset: ReadWrite<u32, Channel::Register>,
64    chenclr: ReadWrite<u32, Channel::Register>,
65    ch0_eep: ReadWrite<u32, EventEndPoint::Register>,
66    ch0_tep: ReadWrite<u32, TaskEndPoint::Register>,
67    ch1_eep: ReadWrite<u32, EventEndPoint::Register>,
68    ch1_tep: ReadWrite<u32, TaskEndPoint::Register>,
69    ch2_eep: ReadWrite<u32, EventEndPoint::Register>,
70    ch2_tep: ReadWrite<u32, TaskEndPoint::Register>,
71    ch3_eep: ReadWrite<u32, EventEndPoint::Register>,
72    ch3_tep: ReadWrite<u32, TaskEndPoint::Register>,
73    ch4_eep: ReadWrite<u32, EventEndPoint::Register>,
74    ch4_tep: ReadWrite<u32, TaskEndPoint::Register>,
75    ch5_eep: ReadWrite<u32, EventEndPoint::Register>,
76    ch5_tep: ReadWrite<u32, TaskEndPoint::Register>,
77    ch6_eep: ReadWrite<u32, EventEndPoint::Register>,
78    ch6_tep: ReadWrite<u32, TaskEndPoint::Register>,
79    ch7_eep: ReadWrite<u32, EventEndPoint::Register>,
80    ch7_tep: ReadWrite<u32, TaskEndPoint::Register>,
81    ch8_eep: ReadWrite<u32, EventEndPoint::Register>,
82    ch8_tep: ReadWrite<u32, TaskEndPoint::Register>,
83    ch9_eep: ReadWrite<u32, EventEndPoint::Register>,
84    ch9_tep: ReadWrite<u32, TaskEndPoint::Register>,
85    ch10_eep: ReadWrite<u32, EventEndPoint::Register>,
86    ch10_tep: ReadWrite<u32, TaskEndPoint::Register>,
87    ch11_eep: ReadWrite<u32, EventEndPoint::Register>,
88    ch11_tep: ReadWrite<u32, TaskEndPoint::Register>,
89    ch12_eep: ReadWrite<u32, EventEndPoint::Register>,
90    ch12_tep: ReadWrite<u32, TaskEndPoint::Register>,
91    ch13_eep: ReadWrite<u32, EventEndPoint::Register>,
92    ch13_tep: ReadWrite<u32, TaskEndPoint::Register>,
93    ch14_eep: ReadWrite<u32, EventEndPoint::Register>,
94    ch14_tep: ReadWrite<u32, TaskEndPoint::Register>,
95    ch15_eep: ReadWrite<u32, EventEndPoint::Register>,
96    ch15_tep: ReadWrite<u32, TaskEndPoint::Register>,
97    ch16_eep: ReadWrite<u32, EventEndPoint::Register>,
98    ch16_tep: ReadWrite<u32, TaskEndPoint::Register>,
99    ch17_eep: ReadWrite<u32, EventEndPoint::Register>,
100    ch17_tep: ReadWrite<u32, TaskEndPoint::Register>,
101    ch18_eep: ReadWrite<u32, EventEndPoint::Register>,
102    ch18_tep: ReadWrite<u32, TaskEndPoint::Register>,
103    ch19_eep: ReadWrite<u32, EventEndPoint::Register>,
104    ch19_tep: ReadWrite<u32, TaskEndPoint::Register>,
105    _reserved2: [u32; 148],
106    chg: [ReadWrite<u32, Channel::Register>; 6],
107    _reserved3: [u32; 62],
108    fork_tep: [ReadWrite<u32, TaskEndPoint::Register>; 32],
109}
110
111register_bitfields! [u32,
112    Control [
113        ENABLE OFFSET(0) NUMBITS(1)
114    ],
115    pub Channel [
116         CH0 OFFSET(0) NUMBITS(1),
117         CH1 OFFSET(1) NUMBITS(1),
118         CH2 OFFSET(2) NUMBITS(1),
119         CH3 OFFSET(3) NUMBITS(1),
120         CH4 OFFSET(4) NUMBITS(1),
121         CH5 OFFSET(5) NUMBITS(1),
122         CH6 OFFSET(6) NUMBITS(1),
123         CH7 OFFSET(7) NUMBITS(1),
124         CH8 OFFSET(8) NUMBITS(1),
125         CH9 OFFSET(9) NUMBITS(1),
126         CH10 OFFSET(10) NUMBITS(1),
127         CH11 OFFSET(11) NUMBITS(1),
128         CH12 OFFSET(12) NUMBITS(1),
129         CH13 OFFSET(13) NUMBITS(1),
130         CH14 OFFSET(14) NUMBITS(1),
131         CH15 OFFSET(15) NUMBITS(1),
132         CH16 OFFSET(16) NUMBITS(1),
133         CH17 OFFSET(17) NUMBITS(1),
134         CH18 OFFSET(18) NUMBITS(1),
135         CH19 OFFSET(19) NUMBITS(1),
136         CH20 OFFSET(20) NUMBITS(1),
137         CH21 OFFSET(21) NUMBITS(1),
138         CH22 OFFSET(22) NUMBITS(1),
139         CH23 OFFSET(23) NUMBITS(1),
140         CH24 OFFSET(24) NUMBITS(1),
141         CH25 OFFSET(25) NUMBITS(1),
142         CH26 OFFSET(26) NUMBITS(1),
143         CH27 OFFSET(27) NUMBITS(1),
144         CH28 OFFSET(28) NUMBITS(1),
145         CH29 OFFSET(29) NUMBITS(1),
146         CH30 OFFSET(30) NUMBITS(1),
147         CH31 OFFSET(31) NUMBITS(1)
148    ],
149    TaskEndPoint [
150        ADDRESS OFFSET(0) NUMBITS(32)
151    ],
152    EventEndPoint [
153        ADDRESS OFFSET(0) NUMBITS(32)
154    ]
155];
156
157pub struct Ppi {
158    registers: StaticRef<PpiRegisters>,
159}
160
161impl Ppi {
162    pub const fn new() -> Ppi {
163        Ppi {
164            registers: PPI_BASE,
165        }
166    }
167
168    pub fn enable(&self, channels: FieldValue<u32, Channel::Register>) {
169        self.registers.chenset.write(channels);
170    }
171
172    pub fn disable(&self, channels: FieldValue<u32, Channel::Register>) {
173        self.registers.chenclr.write(channels);
174    }
175}
nrf52/ppi.rs

nrf52/
ppi.rs
