lowrisc/registers/
sram_ctrl_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for sram_ctrl.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/sram_ctrl/data/sram_ctrl.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const SRAM_CTRL_PARAM_NUM_ALERTS: u32 = 1;
16/// Register width
17pub const SRAM_CTRL_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub SramCtrlRegisters {
21        /// Alert Test Register
22        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
23        /// SRAM status register.
24        (0x0004 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
25        /// Lock register for execution enable register.
26        (0x0008 => pub(crate) exec_regwen: ReadWrite<u32, EXEC_REGWEN::Register>),
27        /// Sram execution enable.
28        (0x000c => pub(crate) exec: ReadWrite<u32, EXEC::Register>),
29        /// Lock register for control register.
30        (0x0010 => pub(crate) ctrl_regwen: ReadWrite<u32, CTRL_REGWEN::Register>),
31        /// SRAM ctrl register.
32        (0x0014 => pub(crate) ctrl: ReadWrite<u32, CTRL::Register>),
33        (0x0018 => @END),
34    }
35}
36
37register_bitfields![u32,
38    pub(crate) ALERT_TEST [
39        FATAL_ERROR OFFSET(0) NUMBITS(1) [],
40    ],
41    pub(crate) STATUS [
42        BUS_INTEG_ERROR OFFSET(0) NUMBITS(1) [],
43        INIT_ERROR OFFSET(1) NUMBITS(1) [],
44        ESCALATED OFFSET(2) NUMBITS(1) [],
45        SCR_KEY_VALID OFFSET(3) NUMBITS(1) [],
46        SCR_KEY_SEED_VALID OFFSET(4) NUMBITS(1) [],
47        INIT_DONE OFFSET(5) NUMBITS(1) [],
48    ],
49    pub(crate) EXEC_REGWEN [
50        EXEC_REGWEN OFFSET(0) NUMBITS(1) [],
51    ],
52    pub(crate) EXEC [
53        EN OFFSET(0) NUMBITS(4) [],
54    ],
55    pub(crate) CTRL_REGWEN [
56        CTRL_REGWEN OFFSET(0) NUMBITS(1) [],
57    ],
58    pub(crate) CTRL [
59        RENEW_SCR_KEY OFFSET(0) NUMBITS(1) [],
60        INIT OFFSET(1) NUMBITS(1) [],
61    ],
62];
63
64// End generated register constants for sram_ctrl
lowrisc/registers/sram_ctrl_regs.rs

lowrisc/registers/
sram_ctrl_regs.rs
