rp2040/
lib.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5#![no_std]
6
7pub mod adc;
8pub mod chip;
9pub mod clocks;
10mod deferred_calls;
11pub mod gpio;
12pub mod i2c;
13pub mod interrupts;
14pub mod pio;
15pub mod pio_pwm;
16pub mod pwm;
17pub mod resets;
18pub mod rtc;
19pub mod spi;
20pub mod sysinfo;
21pub mod test;
22pub mod timer;
23pub mod uart;
24pub mod usb;
25pub mod watchdog;
26pub mod xosc;
27
28use cortexm0p::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM0P, CortexMVariant};
29
30extern "C" {
31    // _estack is not really a function, but it makes the types work
32    // You should never actually invoke it!!
33    fn _estack();
34}
35
36#[cfg_attr(
37    all(target_arch = "arm", target_os = "none"),
38    link_section = ".vectors"
39)]
40// used Ensures that the symbol is kept until the final binary
41#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
42pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
43    _estack,
44    initialize_ram_jump_to_main,
45    unhandled_interrupt,           // NMI
46    CortexM0P::HARD_FAULT_HANDLER, // Hard Fault
47    unhandled_interrupt,           // MemManage
48    unhandled_interrupt,           // BusFault
49    unhandled_interrupt,           // UsageFault
50    unhandled_interrupt,
51    unhandled_interrupt,
52    unhandled_interrupt,
53    unhandled_interrupt,
54    CortexM0P::SVC_HANDLER, // SVC
55    unhandled_interrupt,    // DebugMon
56    unhandled_interrupt,
57    unhandled_interrupt,        // PendSV
58    CortexM0P::SYSTICK_HANDLER, // SysTick
59];
60
61// RP2040 has total of 26 interrupts, but the SDK declares 32 as 26 - 32 might be manually handled
62#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
63// used Ensures that the symbol is kept until the final binary
64#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
65pub static IRQS: [unsafe extern "C" fn(); 32] = [
66    CortexM0P::GENERIC_ISR, // TIMER0 (0)
67    CortexM0P::GENERIC_ISR, // TIMER1 (1)
68    CortexM0P::GENERIC_ISR, // TIMER2 (2)
69    CortexM0P::GENERIC_ISR, // TIMER3 (3)
70    CortexM0P::GENERIC_ISR, // PWM WRAP (4)
71    CortexM0P::GENERIC_ISR, // USB (5)
72    CortexM0P::GENERIC_ISR, // XIP (6)
73    CortexM0P::GENERIC_ISR, // PIO0 INT0  (7)
74    CortexM0P::GENERIC_ISR, // PIO0 INT1 (8)
75    CortexM0P::GENERIC_ISR, // PIO1 INT0 (9)
76    CortexM0P::GENERIC_ISR, // PIO1 INT1 (10)
77    CortexM0P::GENERIC_ISR, // DMA0 (11)
78    CortexM0P::GENERIC_ISR, // DMA1 (12)
79    CortexM0P::GENERIC_ISR, // IO BANK 0 (13)
80    CortexM0P::GENERIC_ISR, // IO QSPI (14)
81    CortexM0P::GENERIC_ISR, // SIO PROC 0 (15)
82    CortexM0P::GENERIC_ISR, // SIO PROC 1 (16)
83    CortexM0P::GENERIC_ISR, // CLOCKS (17)
84    CortexM0P::GENERIC_ISR, // SPI 0 (18)
85    CortexM0P::GENERIC_ISR, // SPI 1 (19)
86    CortexM0P::GENERIC_ISR, // UART 0 (20)
87    CortexM0P::GENERIC_ISR, // UART 1 (21)
88    CortexM0P::GENERIC_ISR, // ADC FIFO (22)
89    CortexM0P::GENERIC_ISR, // I2C 0 (23)
90    CortexM0P::GENERIC_ISR, // I2C 1 (24)
91    CortexM0P::GENERIC_ISR, // RTC (25)
92    unhandled_interrupt,    // (26)
93    unhandled_interrupt,    // (27)
94    unhandled_interrupt,    // (28)
95    unhandled_interrupt,    // (29)
96    unhandled_interrupt,    // (30)
97    unhandled_interrupt,    // (31)
98];
99
100extern "C" {
101    static mut _szero: usize;
102    static mut _ezero: usize;
103    static mut _etext: usize;
104    static mut _srelocate: usize;
105    static mut _erelocate: usize;
106}
107
108pub unsafe fn init() {
109    cortexm0p::nvic::disable_all();
110    cortexm0p::nvic::clear_all_pending();
111    let sio = gpio::SIO::new();
112    let processor = sio.get_processor();
113    match processor {
114        chip::Processor::Processor0 => {}
115        _ => panic!(
116            "Kernel should run only using processor 0 (now processor {})",
117            processor as u8
118        ),
119    }
120}