earlgrey/registers/
clkmgr_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for clkmgr.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of clock groups
15pub const CLKMGR_PARAM_NUM_GROUPS: u32 = 7;
16/// Number of SW gateable clocks
17pub const CLKMGR_PARAM_NUM_SW_GATEABLE_CLOCKS: u32 = 4;
18/// Number of hintable clocks
19pub const CLKMGR_PARAM_NUM_HINTABLE_CLOCKS: u32 = 4;
20/// Number of alerts
21pub const CLKMGR_PARAM_NUM_ALERTS: u32 = 2;
22/// Register width
23pub const CLKMGR_PARAM_REG_WIDTH: u32 = 32;
24
25register_structs! {
26    pub ClkmgrRegisters {
27        /// Alert Test Register
28        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// External clock control write enable
30        (0x0004 => pub(crate) extclk_ctrl_regwen: ReadWrite<u32, EXTCLK_CTRL_REGWEN::Register>),
31        /// Select external clock
32        (0x0008 => pub(crate) extclk_ctrl: ReadWrite<u32, EXTCLK_CTRL::Register>),
33        /// Status of requested external clock switch
34        (0x000c => pub(crate) extclk_status: ReadWrite<u32, EXTCLK_STATUS::Register>),
35        /// Jitter write enable
36        (0x0010 => pub(crate) jitter_regwen: ReadWrite<u32, JITTER_REGWEN::Register>),
37        /// Enable jittery clock
38        (0x0014 => pub(crate) jitter_enable: ReadWrite<u32, JITTER_ENABLE::Register>),
39        /// Clock enable for software gateable clocks.
40        (0x0018 => pub(crate) clk_enables: ReadWrite<u32, CLK_ENABLES::Register>),
41        /// Clock hint for software gateable transactional clocks during active mode.
42        (0x001c => pub(crate) clk_hints: ReadWrite<u32, CLK_HINTS::Register>),
43        /// Since the final state of !!CLK_HINTS is not always determined by software,
44        (0x0020 => pub(crate) clk_hints_status: ReadWrite<u32, CLK_HINTS_STATUS::Register>),
45        /// Measurement control write enable
46        (0x0024 => pub(crate) measure_ctrl_regwen: ReadWrite<u32, MEASURE_CTRL_REGWEN::Register>),
47        /// Enable for measurement control
48        (0x0028 => pub(crate) io_meas_ctrl_en: ReadWrite<u32, IO_MEAS_CTRL_EN::Register>),
49        /// Configuration controls for io measurement.
50        (0x002c => pub(crate) io_meas_ctrl_shadowed: ReadWrite<u32, IO_MEAS_CTRL_SHADOWED::Register>),
51        /// Enable for measurement control
52        (0x0030 => pub(crate) io_div2_meas_ctrl_en: ReadWrite<u32, IO_DIV2_MEAS_CTRL_EN::Register>),
53        /// Configuration controls for io_div2 measurement.
54        (0x0034 => pub(crate) io_div2_meas_ctrl_shadowed: ReadWrite<u32, IO_DIV2_MEAS_CTRL_SHADOWED::Register>),
55        /// Enable for measurement control
56        (0x0038 => pub(crate) io_div4_meas_ctrl_en: ReadWrite<u32, IO_DIV4_MEAS_CTRL_EN::Register>),
57        /// Configuration controls for io_div4 measurement.
58        (0x003c => pub(crate) io_div4_meas_ctrl_shadowed: ReadWrite<u32, IO_DIV4_MEAS_CTRL_SHADOWED::Register>),
59        /// Enable for measurement control
60        (0x0040 => pub(crate) main_meas_ctrl_en: ReadWrite<u32, MAIN_MEAS_CTRL_EN::Register>),
61        /// Configuration controls for main measurement.
62        (0x0044 => pub(crate) main_meas_ctrl_shadowed: ReadWrite<u32, MAIN_MEAS_CTRL_SHADOWED::Register>),
63        /// Enable for measurement control
64        (0x0048 => pub(crate) usb_meas_ctrl_en: ReadWrite<u32, USB_MEAS_CTRL_EN::Register>),
65        /// Configuration controls for usb measurement.
66        (0x004c => pub(crate) usb_meas_ctrl_shadowed: ReadWrite<u32, USB_MEAS_CTRL_SHADOWED::Register>),
67        /// Recoverable Error code
68        (0x0050 => pub(crate) recov_err_code: ReadWrite<u32, RECOV_ERR_CODE::Register>),
69        /// Error code
70        (0x0054 => pub(crate) fatal_err_code: ReadWrite<u32, FATAL_ERR_CODE::Register>),
71        (0x0058 => @END),
72    }
73}
74
75register_bitfields![u32,
76    pub(crate) ALERT_TEST [
77        RECOV_FAULT OFFSET(0) NUMBITS(1) [],
78        FATAL_FAULT OFFSET(1) NUMBITS(1) [],
79    ],
80    pub(crate) EXTCLK_CTRL_REGWEN [
81        EN OFFSET(0) NUMBITS(1) [],
82    ],
83    pub(crate) EXTCLK_CTRL [
84        SEL OFFSET(0) NUMBITS(4) [],
85        HI_SPEED_SEL OFFSET(4) NUMBITS(4) [],
86    ],
87    pub(crate) EXTCLK_STATUS [
88        ACK OFFSET(0) NUMBITS(4) [],
89    ],
90    pub(crate) JITTER_REGWEN [
91        EN OFFSET(0) NUMBITS(1) [],
92    ],
93    pub(crate) JITTER_ENABLE [
94        VAL OFFSET(0) NUMBITS(4) [],
95    ],
96    pub(crate) CLK_ENABLES [
97        CLK_IO_DIV4_PERI_EN OFFSET(0) NUMBITS(1) [],
98        CLK_IO_DIV2_PERI_EN OFFSET(1) NUMBITS(1) [],
99        CLK_IO_PERI_EN OFFSET(2) NUMBITS(1) [],
100        CLK_USB_PERI_EN OFFSET(3) NUMBITS(1) [],
101    ],
102    pub(crate) CLK_HINTS [
103        CLK_MAIN_AES_HINT OFFSET(0) NUMBITS(1) [],
104        CLK_MAIN_HMAC_HINT OFFSET(1) NUMBITS(1) [],
105        CLK_MAIN_KMAC_HINT OFFSET(2) NUMBITS(1) [],
106        CLK_MAIN_OTBN_HINT OFFSET(3) NUMBITS(1) [],
107    ],
108    pub(crate) CLK_HINTS_STATUS [
109        CLK_MAIN_AES_VAL OFFSET(0) NUMBITS(1) [],
110        CLK_MAIN_HMAC_VAL OFFSET(1) NUMBITS(1) [],
111        CLK_MAIN_KMAC_VAL OFFSET(2) NUMBITS(1) [],
112        CLK_MAIN_OTBN_VAL OFFSET(3) NUMBITS(1) [],
113    ],
114    pub(crate) MEASURE_CTRL_REGWEN [
115        EN OFFSET(0) NUMBITS(1) [],
116    ],
117    pub(crate) IO_MEAS_CTRL_EN [
118        EN OFFSET(0) NUMBITS(4) [],
119    ],
120    pub(crate) IO_MEAS_CTRL_SHADOWED [
121        HI OFFSET(0) NUMBITS(10) [],
122        LO OFFSET(10) NUMBITS(10) [],
123    ],
124    pub(crate) IO_DIV2_MEAS_CTRL_EN [
125        EN OFFSET(0) NUMBITS(4) [],
126    ],
127    pub(crate) IO_DIV2_MEAS_CTRL_SHADOWED [
128        HI OFFSET(0) NUMBITS(9) [],
129        LO OFFSET(9) NUMBITS(9) [],
130    ],
131    pub(crate) IO_DIV4_MEAS_CTRL_EN [
132        EN OFFSET(0) NUMBITS(4) [],
133    ],
134    pub(crate) IO_DIV4_MEAS_CTRL_SHADOWED [
135        HI OFFSET(0) NUMBITS(8) [],
136        LO OFFSET(8) NUMBITS(8) [],
137    ],
138    pub(crate) MAIN_MEAS_CTRL_EN [
139        EN OFFSET(0) NUMBITS(4) [],
140    ],
141    pub(crate) MAIN_MEAS_CTRL_SHADOWED [
142        HI OFFSET(0) NUMBITS(10) [],
143        LO OFFSET(10) NUMBITS(10) [],
144    ],
145    pub(crate) USB_MEAS_CTRL_EN [
146        EN OFFSET(0) NUMBITS(4) [],
147    ],
148    pub(crate) USB_MEAS_CTRL_SHADOWED [
149        HI OFFSET(0) NUMBITS(9) [],
150        LO OFFSET(9) NUMBITS(9) [],
151    ],
152    pub(crate) RECOV_ERR_CODE [
153        SHADOW_UPDATE_ERR OFFSET(0) NUMBITS(1) [],
154        IO_MEASURE_ERR OFFSET(1) NUMBITS(1) [],
155        IO_DIV2_MEASURE_ERR OFFSET(2) NUMBITS(1) [],
156        IO_DIV4_MEASURE_ERR OFFSET(3) NUMBITS(1) [],
157        MAIN_MEASURE_ERR OFFSET(4) NUMBITS(1) [],
158        USB_MEASURE_ERR OFFSET(5) NUMBITS(1) [],
159        IO_TIMEOUT_ERR OFFSET(6) NUMBITS(1) [],
160        IO_DIV2_TIMEOUT_ERR OFFSET(7) NUMBITS(1) [],
161        IO_DIV4_TIMEOUT_ERR OFFSET(8) NUMBITS(1) [],
162        MAIN_TIMEOUT_ERR OFFSET(9) NUMBITS(1) [],
163        USB_TIMEOUT_ERR OFFSET(10) NUMBITS(1) [],
164    ],
165    pub(crate) FATAL_ERR_CODE [
166        REG_INTG OFFSET(0) NUMBITS(1) [],
167        IDLE_CNT OFFSET(1) NUMBITS(1) [],
168        SHADOW_STORAGE_ERR OFFSET(2) NUMBITS(1) [],
169    ],
170];
171
172// End generated register constants for clkmgr
earlgrey/registers/clkmgr_regs.rs

earlgrey/registers/
clkmgr_regs.rs
