x86/registers/
dtables.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2025.
4
5// This is inspired and adapted for Tock from the [x86](https://github.com/gz/rust-x86) crate.
6
7//! Functions and data-structures for working with descriptor tables.
8
9use super::segmentation::SegmentSelector;
10
11#[cfg(target_arch = "x86")]
12use core::arch::asm;
13
14use core::fmt;
15use core::mem::size_of;
16
17/// A struct describing a pointer to a descriptor table (GDT / IDT).
18/// This is in a format suitable for giving to 'lgdt' or 'lidt'.
19#[repr(C, packed)]
20pub struct DescriptorTablePointer<Entry> {
21    /// Size of the DT.
22    pub limit: u16,
23    /// Pointer to the memory region containing the DT.
24    pub base: *const Entry,
25}
26
27impl<T> Default for DescriptorTablePointer<T> {
28    fn default() -> DescriptorTablePointer<T> {
29        DescriptorTablePointer {
30            limit: 0,
31            base: core::ptr::null(),
32        }
33    }
34}
35
36impl<T> DescriptorTablePointer<T> {
37    pub fn new(tbl: &T) -> Self {
38        // GDT, LDT, and IDT all expect the limit to be set to "one less".
39        // See Intel 3a, Section 3.5.1 "Segment Descriptor Tables" and
40        // Section 6.10 "Interrupt Descriptor Table (IDT)".
41        let len = size_of::<T>() - 1;
42        assert!(len < 0x10000);
43        DescriptorTablePointer {
44            base: core::ptr::from_ref::<T>(tbl),
45            limit: len as u16,
46        }
47    }
48
49    pub fn new_from_slice(slice: &[T]) -> Self {
50        // GDT, LDT, and IDT all expect the limit to be set to "one less".
51        // See Intel 3a, Section 3.5.1 "Segment Descriptor Tables" and
52        // Section 6.10 "Interrupt Descriptor Table (IDT)".
53        let len = core::mem::size_of_val(slice) - 1;
54        assert!(len < 0x10000);
55        DescriptorTablePointer {
56            base: slice.as_ptr(),
57            limit: len as u16,
58        }
59    }
60}
61
62impl<T> fmt::Debug for DescriptorTablePointer<T> {
63    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
64        write!(f, "DescriptorTablePointer ({} {:?})", { self.limit }, {
65            self.base
66        })
67    }
68}
69
70/// Load the GDTR register with the specified base and limit.
71///
72/// # Safety
73/// Needs CPL 0.
74#[cfg(target_arch = "x86")]
75pub unsafe fn lgdt<T>(gdt: &DescriptorTablePointer<T>) {
76    unsafe {
77        asm!("lgdt ({0})", in(reg) gdt, options(att_syntax));
78    }
79}
80
81/// Retrieve base and limit from the GDTR register.
82///
83/// # Safety
84/// Needs CPL 0.
85#[cfg(target_arch = "x86")]
86pub unsafe fn sgdt<T>(idt: &mut DescriptorTablePointer<T>) {
87    unsafe {
88        asm!("sgdt ({0})", in(reg) core::ptr::from_mut::<DescriptorTablePointer<T>>(idt), options(att_syntax));
89    }
90}
91
92/// Loads the segment selector into the selector field of the local
93/// descriptor table register (LDTR).
94///
95/// After the segment selector is loaded in the LDTR,
96/// the processor uses the segment selector to locate
97/// the segment descriptor for the LDT in the global
98/// descriptor table (GDT).
99///
100/// # Safety
101/// Needs CPL 0.
102#[cfg(target_arch = "x86")]
103pub unsafe fn load_ldtr(selector: SegmentSelector) {
104    unsafe {
105        asm!("lldt {0:x}", in(reg) selector.bits(), options(att_syntax));
106    }
107}
108
109/// Returns the segment selector from the local descriptor table register (LDTR).
110///
111/// The returned segment selector points to the segment descriptor
112/// (located in the GDT) for the current LDT.
113///
114/// # Safety
115/// Needs CPL 0.
116#[cfg(target_arch = "x86")]
117pub unsafe fn ldtr() -> SegmentSelector {
118    let selector: u16;
119    unsafe {
120        asm!("sldt {0:x}", out(reg) selector, options(att_syntax));
121    }
122    SegmentSelector::from_raw(selector)
123}
124
125/// Load the IDTR register with the specified base and limit.
126///
127/// # Safety
128/// Needs CPL 0.
129#[cfg(target_arch = "x86")]
130pub unsafe fn lidt<T>(idt: &DescriptorTablePointer<T>) {
131    unsafe {
132        asm!("lidt ({0})", in(reg) idt, options(att_syntax));
133    }
134}
135
136/// Retrieve base and limit from the IDTR register.
137///
138/// # Safety
139/// Needs CPL 0.
140#[cfg(target_arch = "x86")]
141pub unsafe fn sidt<T>(idt: &mut DescriptorTablePointer<T>) {
142    unsafe {
143        asm!("sidt ({0})", in(reg) core::ptr::from_mut::<DescriptorTablePointer<T>>(idt), options(att_syntax));
144    }
145}
146
147//For CI only
148
149#[cfg(not(any(doc, target_arch = "x86")))]
150pub unsafe fn lgdt<T>(_gdt: &DescriptorTablePointer<T>) {
151    unimplemented!()
152}
153
154#[cfg(not(any(doc, target_arch = "x86")))]
155pub unsafe fn sgdt<T>(_idt: &mut DescriptorTablePointer<T>) {
156    unimplemented!()
157}
158
159#[cfg(not(any(doc, target_arch = "x86")))]
160pub unsafe fn load_ldtr(_selector: SegmentSelector) {
161    unimplemented!()
162}
163
164#[cfg(not(any(doc, target_arch = "x86")))]
165pub unsafe fn ldtr() -> SegmentSelector {
166    unimplemented!()
167}
168
169#[cfg(not(any(doc, target_arch = "x86")))]
170pub unsafe fn lidt<T>(_idt: &DescriptorTablePointer<T>) {
171    unimplemented!()
172}
173
174#[cfg(not(any(doc, target_arch = "x86")))]
175pub unsafe fn sidt<T>(_idt: &mut DescriptorTablePointer<T>) {
176    unimplemented!()
177}
x86/registers/dtables.rs

x86/registers/
dtables.rs
