earlgrey/registers/
pwrmgr_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for pwrmgr.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of wakeups
15pub const PWRMGR_PARAM_NUM_WKUPS: u32 = 6;
16/// Vector index for sysrst_ctrl_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO
17pub const PWRMGR_PARAM_SYSRST_CTRL_AON_WKUP_REQ_IDX: u32 = 0;
18/// Vector index for adc_ctrl_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO
19pub const PWRMGR_PARAM_ADC_CTRL_AON_WKUP_REQ_IDX: u32 = 1;
20/// Vector index for pinmux_aon pin_wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO
21pub const PWRMGR_PARAM_PINMUX_AON_PIN_WKUP_REQ_IDX: u32 = 2;
22/// Vector index for pinmux_aon usb_wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO
23pub const PWRMGR_PARAM_PINMUX_AON_USB_WKUP_REQ_IDX: u32 = 3;
24/// Vector index for aon_timer_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO
25pub const PWRMGR_PARAM_AON_TIMER_AON_WKUP_REQ_IDX: u32 = 4;
26/// Vector index for sensor_ctrl wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO
27pub const PWRMGR_PARAM_SENSOR_CTRL_WKUP_REQ_IDX: u32 = 5;
28/// Number of peripheral reset requets
29pub const PWRMGR_PARAM_NUM_RST_REQS: u32 = 2;
30/// Number of pwrmgr internal reset requets
31pub const PWRMGR_PARAM_NUM_INT_RST_REQS: u32 = 2;
32/// Number of debug reset requets
33pub const PWRMGR_PARAM_NUM_DEBUG_RST_REQS: u32 = 1;
34/// Reset req idx for MainPwr
35pub const PWRMGR_PARAM_RESET_MAIN_PWR_IDX: u32 = 2;
36/// Reset req idx for Esc
37pub const PWRMGR_PARAM_RESET_ESC_IDX: u32 = 3;
38/// Reset req idx for Ndm
39pub const PWRMGR_PARAM_RESET_NDM_IDX: u32 = 4;
40/// Number of alerts
41pub const PWRMGR_PARAM_NUM_ALERTS: u32 = 1;
42/// Register width
43pub const PWRMGR_PARAM_REG_WIDTH: u32 = 32;
44
45register_structs! {
46    pub PwrmgrRegisters {
47        /// Interrupt State Register
48        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
49        /// Interrupt Enable Register
50        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
51        /// Interrupt Test Register
52        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
53        /// Alert Test Register
54        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
55        /// Controls the configurability of the !!CONTROL register.
56        (0x0010 => pub(crate) ctrl_cfg_regwen: ReadWrite<u32, CTRL_CFG_REGWEN::Register>),
57        /// Control register
58        (0x0014 => pub(crate) control: ReadWrite<u32, CONTROL::Register>),
59        /// The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the
60        (0x0018 => pub(crate) cfg_cdc_sync: ReadWrite<u32, CFG_CDC_SYNC::Register>),
61        /// Configuration enable for wakeup_en register
62        (0x001c => pub(crate) wakeup_en_regwen: ReadWrite<u32, WAKEUP_EN_REGWEN::Register>),
63        /// Bit mask for enabled wakeups
64        (0x0020 => pub(crate) wakeup_en: [ReadWrite<u32, WAKEUP_EN::Register>; 1]),
65        /// A read only register of all current wake requests post enable mask
66        (0x0024 => pub(crate) wake_status: [ReadWrite<u32, WAKE_STATUS::Register>; 1]),
67        /// Configuration enable for reset_en register
68        (0x0028 => pub(crate) reset_en_regwen: ReadWrite<u32, RESET_EN_REGWEN::Register>),
69        /// Bit mask for enabled reset requests
70        (0x002c => pub(crate) reset_en: [ReadWrite<u32, RESET_EN::Register>; 1]),
71        /// A read only register of all current reset requests post enable mask
72        (0x0030 => pub(crate) reset_status: [ReadWrite<u32, RESET_STATUS::Register>; 1]),
73        /// A read only register of escalation reset request
74        (0x0034 => pub(crate) escalate_reset_status: ReadWrite<u32, ESCALATE_RESET_STATUS::Register>),
75        /// Indicates which functions caused the chip to wakeup
76        (0x0038 => pub(crate) wake_info_capture_dis: ReadWrite<u32, WAKE_INFO_CAPTURE_DIS::Register>),
77        /// Indicates which functions caused the chip to wakeup.
78        (0x003c => pub(crate) wake_info: ReadWrite<u32, WAKE_INFO::Register>),
79        /// A read only register that shows the existing faults
80        (0x0040 => pub(crate) fault_status: ReadWrite<u32, FAULT_STATUS::Register>),
81        (0x0044 => @END),
82    }
83}
84
85register_bitfields![u32,
86    /// Common Interrupt Offsets
87    pub(crate) INTR [
88        WAKEUP OFFSET(0) NUMBITS(1) [],
89    ],
90    pub(crate) ALERT_TEST [
91        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
92    ],
93    pub(crate) CTRL_CFG_REGWEN [
94        EN OFFSET(0) NUMBITS(1) [],
95    ],
96    pub(crate) CONTROL [
97        LOW_POWER_HINT OFFSET(0) NUMBITS(1) [
98            NONE = 0,
99            LOW_POWER = 1,
100        ],
101        CORE_CLK_EN OFFSET(4) NUMBITS(1) [
102            DISABLED = 0,
103            ENABLED = 1,
104        ],
105        IO_CLK_EN OFFSET(5) NUMBITS(1) [
106            DISABLED = 0,
107            ENABLED = 1,
108        ],
109        USB_CLK_EN_LP OFFSET(6) NUMBITS(1) [
110            DISABLED = 0,
111            ENABLED = 1,
112        ],
113        USB_CLK_EN_ACTIVE OFFSET(7) NUMBITS(1) [
114            DISABLED = 0,
115            ENABLED = 1,
116        ],
117        MAIN_PD_N OFFSET(8) NUMBITS(1) [
118            POWER_DOWN = 0,
119            POWER_UP = 1,
120        ],
121    ],
122    pub(crate) CFG_CDC_SYNC [
123        SYNC OFFSET(0) NUMBITS(1) [],
124    ],
125    pub(crate) WAKEUP_EN_REGWEN [
126        EN OFFSET(0) NUMBITS(1) [],
127    ],
128    pub(crate) WAKEUP_EN [
129        EN_0 OFFSET(0) NUMBITS(1) [],
130        EN_1 OFFSET(1) NUMBITS(1) [],
131        EN_2 OFFSET(2) NUMBITS(1) [],
132        EN_3 OFFSET(3) NUMBITS(1) [],
133        EN_4 OFFSET(4) NUMBITS(1) [],
134        EN_5 OFFSET(5) NUMBITS(1) [],
135    ],
136    pub(crate) WAKE_STATUS [
137        VAL_0 OFFSET(0) NUMBITS(1) [],
138        VAL_1 OFFSET(1) NUMBITS(1) [],
139        VAL_2 OFFSET(2) NUMBITS(1) [],
140        VAL_3 OFFSET(3) NUMBITS(1) [],
141        VAL_4 OFFSET(4) NUMBITS(1) [],
142        VAL_5 OFFSET(5) NUMBITS(1) [],
143    ],
144    pub(crate) RESET_EN_REGWEN [
145        EN OFFSET(0) NUMBITS(1) [],
146    ],
147    pub(crate) RESET_EN [
148        EN_0 OFFSET(0) NUMBITS(1) [],
149        EN_1 OFFSET(1) NUMBITS(1) [],
150    ],
151    pub(crate) RESET_STATUS [
152        VAL_0 OFFSET(0) NUMBITS(1) [],
153        VAL_1 OFFSET(1) NUMBITS(1) [],
154    ],
155    pub(crate) ESCALATE_RESET_STATUS [
156        VAL OFFSET(0) NUMBITS(1) [],
157    ],
158    pub(crate) WAKE_INFO_CAPTURE_DIS [
159        VAL OFFSET(0) NUMBITS(1) [],
160    ],
161    pub(crate) WAKE_INFO [
162        REASONS OFFSET(0) NUMBITS(6) [],
163        FALL_THROUGH OFFSET(6) NUMBITS(1) [],
164        ABORT OFFSET(7) NUMBITS(1) [],
165    ],
166    pub(crate) FAULT_STATUS [
167        REG_INTG_ERR OFFSET(0) NUMBITS(1) [],
168        ESC_TIMEOUT OFFSET(1) NUMBITS(1) [],
169        MAIN_PD_GLITCH OFFSET(2) NUMBITS(1) [],
170    ],
171];
172
173// End generated register constants for pwrmgr
earlgrey/registers/pwrmgr_regs.rs

earlgrey/registers/
pwrmgr_regs.rs
