1#![crate_name = "imxrt10xx"]
10#![crate_type = "rlib"]
11#![no_std]
12
13pub mod chip;
14pub mod nvic;
15
16pub mod ccm;
18pub mod ccm_analog;
19pub mod dcdc;
20pub mod dma;
21pub mod gpio;
22pub mod gpt;
23pub mod iomuxc;
24pub mod iomuxc_snvs;
25pub mod lpi2c;
26pub mod lpuart;
27
28use cortexm7::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM7, CortexMVariant};
29
30extern "C" {
31 fn _estack();
34}
35
36#[cfg_attr(
37 all(target_arch = "arm", target_os = "none"),
38 link_section = ".vectors"
39)]
40#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
42pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
43 _estack,
44 initialize_ram_jump_to_main,
45 unhandled_interrupt, CortexM7::HARD_FAULT_HANDLER, unhandled_interrupt, unhandled_interrupt, unhandled_interrupt, unhandled_interrupt,
51 unhandled_interrupt,
52 unhandled_interrupt,
53 unhandled_interrupt,
54 CortexM7::SVC_HANDLER, unhandled_interrupt, unhandled_interrupt,
57 unhandled_interrupt, CortexM7::SYSTICK_HANDLER, ];
60
61#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
63#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
65pub static IRQS: [unsafe extern "C" fn(); 160] = [
66 CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, ];
227
228pub unsafe fn init() {
229 cortexm7::nvic::disable_all();
230 cortexm7::nvic::clear_all_pending();
231
232 cortexm7::scb::set_vector_table_offset(core::ptr::addr_of!(BASE_VECTORS) as *const ());
233
234 cortexm7::nvic::enable_all();
235}