imxrt10xx/
lib.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Peripheral implementations for the IMXRT1050 and IMXRT1060 MCUs.
6//!
7//! imxrt1050 chip: <https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1050-evaluation-kit:MIMXRT1050-EVK>
8
9#![crate_name = "imxrt10xx"]
10#![crate_type = "rlib"]
11#![no_std]
12
13pub mod chip;
14pub mod nvic;
15
16// Peripherals
17pub mod ccm;
18pub mod ccm_analog;
19pub mod dcdc;
20pub mod dma;
21pub mod gpio;
22pub mod gpt;
23pub mod iomuxc;
24pub mod iomuxc_snvs;
25pub mod lpi2c;
26pub mod lpuart;
27
28use cortexm7::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM7, CortexMVariant};
29
30extern "C" {
31    // _estack is not really a function, but it makes the types work
32    // You should never actually invoke it!!
33    fn _estack();
34}
35
36#[cfg_attr(
37    all(target_arch = "arm", target_os = "none"),
38    link_section = ".vectors"
39)]
40// used Ensures that the symbol is kept until the final binary
41#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
42pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
43    _estack,
44    initialize_ram_jump_to_main,
45    unhandled_interrupt,          // NMI
46    CortexM7::HARD_FAULT_HANDLER, // Hard Fault
47    unhandled_interrupt,          // MemManage
48    unhandled_interrupt,          // BusFault
49    unhandled_interrupt,          // UsageFault
50    unhandled_interrupt,
51    unhandled_interrupt,
52    unhandled_interrupt,
53    unhandled_interrupt,
54    CortexM7::SVC_HANDLER, // SVC
55    unhandled_interrupt,   // DebugMon
56    unhandled_interrupt,
57    unhandled_interrupt,       // PendSV
58    CortexM7::SYSTICK_HANDLER, // SysTick
59];
60
61// imxrt 1050 has total of 160 interrupts
62#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
63// used Ensures that the symbol is kept until the final binary
64#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
65pub static IRQS: [unsafe extern "C" fn(); 160] = [
66    CortexM7::GENERIC_ISR, // eDMA (0)
67    CortexM7::GENERIC_ISR, // eDMA (1)
68    CortexM7::GENERIC_ISR, // eDMA (2)
69    CortexM7::GENERIC_ISR, // eDMA (3)
70    CortexM7::GENERIC_ISR, // eDMA (4)
71    CortexM7::GENERIC_ISR, // eDMA (5)
72    CortexM7::GENERIC_ISR, // eDMA (6)
73    CortexM7::GENERIC_ISR, // eDMA (7)
74    CortexM7::GENERIC_ISR, // eDMA (8)
75    CortexM7::GENERIC_ISR, // eDMA (9)
76    CortexM7::GENERIC_ISR, // eDMA (10)
77    CortexM7::GENERIC_ISR, // eDMA (11)
78    CortexM7::GENERIC_ISR, // eDMA (12)
79    CortexM7::GENERIC_ISR, // eDMA (13)
80    CortexM7::GENERIC_ISR, // eDMA (14)
81    CortexM7::GENERIC_ISR, // eDMA (15)
82    CortexM7::GENERIC_ISR, // Error_interrupt (16)
83    CortexM7::GENERIC_ISR, // CM7 (17)
84    CortexM7::GENERIC_ISR, // CM7 (18)
85    CortexM7::GENERIC_ISR, // CM7 (19)
86    CortexM7::GENERIC_ISR, // LPUART1 (20)
87    CortexM7::GENERIC_ISR, // LPUART2 (21)
88    CortexM7::GENERIC_ISR, // LPUART3 (22)
89    CortexM7::GENERIC_ISR, // LPUART4 (23)
90    CortexM7::GENERIC_ISR, // LPUART5 (24)
91    CortexM7::GENERIC_ISR, // LPUART6 (25)
92    CortexM7::GENERIC_ISR, // LPUART7 (26)
93    CortexM7::GENERIC_ISR, // LPUART8 (27)
94    CortexM7::GENERIC_ISR, // LPI2C1 (28)
95    CortexM7::GENERIC_ISR, // LPI2C2 (29)
96    CortexM7::GENERIC_ISR, // LPI2C3 (30)
97    CortexM7::GENERIC_ISR, // LPI2C4 (31)
98    CortexM7::GENERIC_ISR, // LPSPI1 (32)
99    CortexM7::GENERIC_ISR, // LPSPI2 (33)
100    CortexM7::GENERIC_ISR, // LPSPI3 (34)
101    CortexM7::GENERIC_ISR, // LPSPI4 (35)
102    CortexM7::GENERIC_ISR, // FLEXCAN1 (36)
103    CortexM7::GENERIC_ISR, // FLEXCAN2 (37)
104    CortexM7::GENERIC_ISR, // CM7 (38)
105    CortexM7::GENERIC_ISR, // KPP (39)
106    CortexM7::GENERIC_ISR, // TSC_DIG (40)
107    CortexM7::GENERIC_ISR, // GPR_IRQ (41)
108    CortexM7::GENERIC_ISR, // LCDIF (42)
109    CortexM7::GENERIC_ISR, // CSI (43)
110    CortexM7::GENERIC_ISR, // PXP (44)
111    CortexM7::GENERIC_ISR, // WDOG2 (45)
112    CortexM7::GENERIC_ISR, // SNVS_HP_WRAPPER (46)
113    CortexM7::GENERIC_ISR, // SNVS_HP_WRAPPER (47)
114    CortexM7::GENERIC_ISR, // SNVS_HP_WRAPPER / SNVS_LP_WRAPPER (48)
115    CortexM7::GENERIC_ISR, // CSU (49)
116    CortexM7::GENERIC_ISR, // DCP (50)
117    CortexM7::GENERIC_ISR, // DCP (51)
118    CortexM7::GENERIC_ISR, // DCP (52)
119    CortexM7::GENERIC_ISR, // TRNG (53)
120    CortexM7::GENERIC_ISR, // Reserved (54)
121    CortexM7::GENERIC_ISR, // BEE (55)
122    CortexM7::GENERIC_ISR, // SAI1 (56)
123    CortexM7::GENERIC_ISR, // SAI2 (57)
124    CortexM7::GENERIC_ISR, // SAI3 (58)
125    CortexM7::GENERIC_ISR, // SAI3 (59)
126    CortexM7::GENERIC_ISR, // SPDIF (60)
127    CortexM7::GENERIC_ISR, // PMU (61)
128    CortexM7::GENERIC_ISR, // Reserved (62)
129    CortexM7::GENERIC_ISR, // Temperature Monitor (63)
130    CortexM7::GENERIC_ISR, // Temperature Monitor (64)
131    CortexM7::GENERIC_ISR, // USB PHY (65)
132    CortexM7::GENERIC_ISR, // USB PHY (66)
133    CortexM7::GENERIC_ISR, // ADC1 (67)
134    CortexM7::GENERIC_ISR, // ADC2 (68)
135    CortexM7::GENERIC_ISR, // DCDC (69)
136    CortexM7::GENERIC_ISR, // Reserved (70)
137    CortexM7::GENERIC_ISR, // Reserved (71)
138    CortexM7::GENERIC_ISR, // GPIO1 (72)
139    CortexM7::GENERIC_ISR, // GPIO1 (73)
140    CortexM7::GENERIC_ISR, // GPIO1 (74)
141    CortexM7::GENERIC_ISR, // GPIO1 (75)
142    CortexM7::GENERIC_ISR, // GPIO1 (76)
143    CortexM7::GENERIC_ISR, // GPIO1 (77)
144    CortexM7::GENERIC_ISR, // GPIO1 (78)
145    CortexM7::GENERIC_ISR, // GPIO1 (79)
146    CortexM7::GENERIC_ISR, // GPIO1_1 (80)
147    CortexM7::GENERIC_ISR, // GPIO1_2 (81)
148    CortexM7::GENERIC_ISR, // GPIO2_1 (82)
149    CortexM7::GENERIC_ISR, // GPIO2_2 (83)
150    CortexM7::GENERIC_ISR, // GPIO3_1 (84)
151    CortexM7::GENERIC_ISR, // GPIO3_2 (85)
152    CortexM7::GENERIC_ISR, // GPIO4_1 (86)
153    CortexM7::GENERIC_ISR, // GPIO4_2 (87)
154    CortexM7::GENERIC_ISR, // GPIO5_1 (88)
155    CortexM7::GENERIC_ISR, // GPIO5_2 (89)
156    CortexM7::GENERIC_ISR, // FLEXIO1 (90)
157    CortexM7::GENERIC_ISR, // FLEXIO2 (91)
158    CortexM7::GENERIC_ISR, // WDOG1 (92)
159    CortexM7::GENERIC_ISR, // RTWDOG (93)
160    CortexM7::GENERIC_ISR, // EWM (94)
161    CortexM7::GENERIC_ISR, // CCM (95)
162    CortexM7::GENERIC_ISR, // CCM (96)
163    CortexM7::GENERIC_ISR, // GPC (97)
164    CortexM7::GENERIC_ISR, // SRC (98)
165    CortexM7::GENERIC_ISR, // Reserved (99)
166    CortexM7::GENERIC_ISR, // GPT1 (100)
167    CortexM7::GENERIC_ISR, // GPT2 (101)
168    CortexM7::GENERIC_ISR, // FLEXPWM1 (102)
169    CortexM7::GENERIC_ISR, // FLEXPWM1 (103)
170    CortexM7::GENERIC_ISR, // FLEXPWM1 (104)
171    CortexM7::GENERIC_ISR, // FLEXPWM1 (105)
172    CortexM7::GENERIC_ISR, // FLEXPWM1 (106)
173    CortexM7::GENERIC_ISR, // Reserved (107)
174    CortexM7::GENERIC_ISR, // FLEXSPI (108)
175    CortexM7::GENERIC_ISR, // SEMC (109)
176    CortexM7::GENERIC_ISR, // USDHC1 (110)
177    CortexM7::GENERIC_ISR, // USDHC2 (111)
178    CortexM7::GENERIC_ISR, // USB (112)
179    CortexM7::GENERIC_ISR, // USB (113)
180    CortexM7::GENERIC_ISR, // ENET (114)
181    CortexM7::GENERIC_ISR, // ENET (115)
182    CortexM7::GENERIC_ISR, // XBAR1 (116)
183    CortexM7::GENERIC_ISR, // XBAR1 (117)
184    CortexM7::GENERIC_ISR, // ADC_ETC (118)
185    CortexM7::GENERIC_ISR, // ADC_ETC (119)
186    CortexM7::GENERIC_ISR, // ADC_ETC (120)
187    CortexM7::GENERIC_ISR, // ADC_ETC (121)
188    CortexM7::GENERIC_ISR, // PIT (122)
189    CortexM7::GENERIC_ISR, // ACMP (123)
190    CortexM7::GENERIC_ISR, // ACMP (124)
191    CortexM7::GENERIC_ISR, // ACMP (125)
192    CortexM7::GENERIC_ISR, // ACMP (126)
193    CortexM7::GENERIC_ISR, // Reserved (127)
194    CortexM7::GENERIC_ISR, // Reserved (128)
195    CortexM7::GENERIC_ISR, // ENC1 (129)
196    CortexM7::GENERIC_ISR, // ENC2 (130)
197    CortexM7::GENERIC_ISR, // ENC3 (131)
198    CortexM7::GENERIC_ISR, // ENC4 (132)
199    CortexM7::GENERIC_ISR, // QTIMER1 (133)
200    CortexM7::GENERIC_ISR, // QTIMER2 (134)
201    CortexM7::GENERIC_ISR, // QTIMER3 (135)
202    CortexM7::GENERIC_ISR, // QTIMER4 (136)
203    CortexM7::GENERIC_ISR, // FLEXPWM2 (137)
204    CortexM7::GENERIC_ISR, // FLEXPWM2 (138)
205    CortexM7::GENERIC_ISR, // FLEXPWM2 (139)
206    CortexM7::GENERIC_ISR, // FLEXPWM2 (140)
207    CortexM7::GENERIC_ISR, // FLEXPWM2 (141)
208    CortexM7::GENERIC_ISR, // FLEXPWM3 (142)
209    CortexM7::GENERIC_ISR, // FLEXPWM3 (143)
210    CortexM7::GENERIC_ISR, // FLEXPWM3 (144)
211    CortexM7::GENERIC_ISR, // FLEXPWM3 (145)
212    CortexM7::GENERIC_ISR, // FLEXPWM3 (146)
213    CortexM7::GENERIC_ISR, // FLEXPWM4 (147)
214    CortexM7::GENERIC_ISR, // FLEXPWM4 (148)
215    CortexM7::GENERIC_ISR, // FLEXPWM4 (149)
216    CortexM7::GENERIC_ISR, // FLEXPWM4 (150)
217    CortexM7::GENERIC_ISR, // FLEXPWM4 (151)
218    CortexM7::GENERIC_ISR, // Reserved (152)
219    CortexM7::GENERIC_ISR, // Reserved (153)
220    CortexM7::GENERIC_ISR, // Reserved (154)
221    CortexM7::GENERIC_ISR, // Reserved (155)
222    CortexM7::GENERIC_ISR, // Reserved (156)
223    CortexM7::GENERIC_ISR, // Reserved (157)
224    CortexM7::GENERIC_ISR, // Reserved (158)
225    CortexM7::GENERIC_ISR, // Reserved (159)
226];
227
228pub unsafe fn init() {
229    cortexm7::nvic::disable_all();
230    cortexm7::nvic::clear_all_pending();
231
232    cortexm7::scb::set_vector_table_offset(core::ptr::addr_of!(BASE_VECTORS) as *const ());
233
234    cortexm7::nvic::enable_all();
235}
imxrt10xx/lib.rs

imxrt10xx/
lib.rs
