1#![no_std]
10
11pub mod chip;
12pub mod nvic;
13
14pub mod ccm;
16pub mod ccm_analog;
17pub mod dcdc;
18pub mod dma;
19pub mod gpio;
20pub mod gpt;
21pub mod iomuxc;
22pub mod iomuxc_snvs;
23pub mod lpi2c;
24pub mod lpuart;
25
26use cortexm7::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM7, CortexMVariant};
27
28extern "C" {
29 fn _estack();
32}
33
34#[cfg_attr(
35 all(target_arch = "arm", target_os = "none"),
36 link_section = ".vectors"
37)]
38#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
40pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
41 _estack,
42 initialize_ram_jump_to_main,
43 unhandled_interrupt, CortexM7::HARD_FAULT_HANDLER, unhandled_interrupt, unhandled_interrupt, unhandled_interrupt, unhandled_interrupt,
49 unhandled_interrupt,
50 unhandled_interrupt,
51 unhandled_interrupt,
52 CortexM7::SVC_HANDLER, unhandled_interrupt, unhandled_interrupt,
55 unhandled_interrupt, CortexM7::SYSTICK_HANDLER, ];
58
59#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
61#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
63pub static IRQS: [unsafe extern "C" fn(); 160] = [
64 CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, CortexM7::GENERIC_ISR, ];
225
226pub unsafe fn init() {
227 cortexm7::nvic::disable_all();
228 cortexm7::nvic::clear_all_pending();
229
230 cortexm7::scb::set_vector_table_offset(core::ptr::addr_of!(BASE_VECTORS) as *const ());
231
232 cortexm7::nvic::enable_all();
233}