lowrisc/registers/
uart_regs.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for uart.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/uart/data/uart.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const UART_PARAM_NUM_ALERTS: u32 = 1;
16/// Register width
17pub const UART_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub UartRegisters {
21        /// Interrupt State Register
22        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
23        /// Interrupt Enable Register
24        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Test Register
26        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
27        /// Alert Test Register
28        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// UART control register
30        (0x0010 => pub(crate) ctrl: ReadWrite<u32, CTRL::Register>),
31        /// UART live status register
32        (0x0014 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
33        /// UART read data
34        (0x0018 => pub(crate) rdata: ReadWrite<u32, RDATA::Register>),
35        /// UART write data
36        (0x001c => pub(crate) wdata: ReadWrite<u32, WDATA::Register>),
37        /// UART FIFO control register
38        (0x0020 => pub(crate) fifo_ctrl: ReadWrite<u32, FIFO_CTRL::Register>),
39        /// UART FIFO status register
40        (0x0024 => pub(crate) fifo_status: ReadWrite<u32, FIFO_STATUS::Register>),
41        /// TX pin override control. Gives direct SW control over TX pin state
42        (0x0028 => pub(crate) ovrd: ReadWrite<u32, OVRD::Register>),
43        /// UART oversampled values
44        (0x002c => pub(crate) val: ReadWrite<u32, VAL::Register>),
45        /// UART RX timeout control
46        (0x0030 => pub(crate) timeout_ctrl: ReadWrite<u32, TIMEOUT_CTRL::Register>),
47        (0x0034 => @END),
48    }
49}
50
51register_bitfields![u32,
52    /// Common Interrupt Offsets
53    pub(crate) INTR [
54        TX_WATERMARK OFFSET(0) NUMBITS(1) [],
55        RX_WATERMARK OFFSET(1) NUMBITS(1) [],
56        TX_EMPTY OFFSET(2) NUMBITS(1) [],
57        RX_OVERFLOW OFFSET(3) NUMBITS(1) [],
58        RX_FRAME_ERR OFFSET(4) NUMBITS(1) [],
59        RX_BREAK_ERR OFFSET(5) NUMBITS(1) [],
60        RX_TIMEOUT OFFSET(6) NUMBITS(1) [],
61        RX_PARITY_ERR OFFSET(7) NUMBITS(1) [],
62    ],
63    pub(crate) ALERT_TEST [
64        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
65    ],
66    pub(crate) CTRL [
67        TX OFFSET(0) NUMBITS(1) [],
68        RX OFFSET(1) NUMBITS(1) [],
69        NF OFFSET(2) NUMBITS(1) [],
70        SLPBK OFFSET(4) NUMBITS(1) [],
71        LLPBK OFFSET(5) NUMBITS(1) [],
72        PARITY_EN OFFSET(6) NUMBITS(1) [],
73        PARITY_ODD OFFSET(7) NUMBITS(1) [],
74        RXBLVL OFFSET(8) NUMBITS(2) [
75            BREAK2 = 0,
76            BREAK4 = 1,
77            BREAK8 = 2,
78            BREAK16 = 3,
79        ],
80        NCO OFFSET(16) NUMBITS(16) [],
81    ],
82    pub(crate) STATUS [
83        TXFULL OFFSET(0) NUMBITS(1) [],
84        RXFULL OFFSET(1) NUMBITS(1) [],
85        TXEMPTY OFFSET(2) NUMBITS(1) [],
86        TXIDLE OFFSET(3) NUMBITS(1) [],
87        RXIDLE OFFSET(4) NUMBITS(1) [],
88        RXEMPTY OFFSET(5) NUMBITS(1) [],
89    ],
90    pub(crate) RDATA [
91        RDATA OFFSET(0) NUMBITS(8) [],
92    ],
93    pub(crate) WDATA [
94        WDATA OFFSET(0) NUMBITS(8) [],
95    ],
96    pub(crate) FIFO_CTRL [
97        RXRST OFFSET(0) NUMBITS(1) [],
98        TXRST OFFSET(1) NUMBITS(1) [],
99        RXILVL OFFSET(2) NUMBITS(3) [
100            RXLVL1 = 0,
101            RXLVL2 = 1,
102            RXLVL4 = 2,
103            RXLVL8 = 3,
104            RXLVL16 = 4,
105            RXLVL32 = 5,
106            RXLVL64 = 6,
107            RXLVL126 = 7,
108        ],
109        TXILVL OFFSET(5) NUMBITS(3) [
110            TXLVL1 = 0,
111            TXLVL2 = 1,
112            TXLVL4 = 2,
113            TXLVL8 = 3,
114            TXLVL16 = 4,
115            TXLVL32 = 5,
116            TXLVL64 = 6,
117        ],
118    ],
119    pub(crate) FIFO_STATUS [
120        TXLVL OFFSET(0) NUMBITS(8) [],
121        RXLVL OFFSET(16) NUMBITS(8) [],
122    ],
123    pub(crate) OVRD [
124        TXEN OFFSET(0) NUMBITS(1) [],
125        TXVAL OFFSET(1) NUMBITS(1) [],
126    ],
127    pub(crate) VAL [
128        RX OFFSET(0) NUMBITS(16) [],
129    ],
130    pub(crate) TIMEOUT_CTRL [
131        VAL OFFSET(0) NUMBITS(24) [],
132        EN OFFSET(31) NUMBITS(1) [],
133    ],
134];
135
136// End generated register constants for uart
lowrisc/registers/uart_regs.rs

lowrisc/registers/
uart_regs.rs
