stm32f4xx/
dbg.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use kernel::utilities::registers::interfaces::ReadWriteable;
6use kernel::utilities::registers::{register_bitfields, ReadOnly, ReadWrite};
7use kernel::utilities::StaticRef;
8
9/// Debug support
10#[repr(C)]
11struct DbgRegisters {
12    /// IDCODE
13    dbgmcu_idcode: ReadOnly<u32, DBGMCU_IDCODE::Register>,
14    /// Control Register
15    dbgmcu_cr: ReadWrite<u32, DBGMCU_CR::Register>,
16    /// Debug MCU APB1 Freeze registe
17    dbgmcu_apb1_fz: ReadWrite<u32, DBGMCU_APB1_FZ::Register>,
18    /// Debug MCU APB2 Freeze registe
19    dbgmcu_apb2_fz: ReadWrite<u32, DBGMCU_APB2_FZ::Register>,
20}
21
22register_bitfields![u32,
23    DBGMCU_IDCODE [
24        /// DEV_ID
25        DEV_ID OFFSET(0) NUMBITS(12) [],
26        /// REV_ID
27        REV_ID OFFSET(16) NUMBITS(16) []
28    ],
29    DBGMCU_CR [
30        /// DBG_SLEEP
31        DBG_SLEEP OFFSET(0) NUMBITS(1) [],
32        /// DBG_STOP
33        DBG_STOP OFFSET(1) NUMBITS(1) [],
34        /// DBG_STANDBY
35        DBG_STANDBY OFFSET(2) NUMBITS(1) [],
36        /// TRACE_IOEN
37        TRACE_IOEN OFFSET(5) NUMBITS(1) [],
38        /// TRACE_MODE
39        TRACE_MODE OFFSET(6) NUMBITS(2) []
40    ],
41    DBGMCU_APB1_FZ [
42        /// DBG_TIM2_STOP
43        DBG_TIM2_STOP OFFSET(0) NUMBITS(1) [],
44        /// DBG_TIM3 _STOP
45        DBG_TIM3_STOP OFFSET(1) NUMBITS(1) [],
46        /// DBG_TIM4_STOP
47        DBG_TIM4_STOP OFFSET(2) NUMBITS(1) [],
48        /// DBG_TIM5_STOP
49        DBG_TIM5_STOP OFFSET(3) NUMBITS(1) [],
50        /// DBG_TIM6_STOP
51        DBG_TIM6_STOP OFFSET(4) NUMBITS(1) [],
52        /// DBG_TIM7_STOP
53        DBG_TIM7_STOP OFFSET(5) NUMBITS(1) [],
54        /// DBG_TIM12_STOP
55        DBG_TIM12_STOP OFFSET(6) NUMBITS(1) [],
56        /// DBG_TIM13_STOP
57        DBG_TIM13_STOP OFFSET(7) NUMBITS(1) [],
58        /// DBG_TIM14_STOP
59        DBG_TIM14_STOP OFFSET(8) NUMBITS(1) [],
60        /// RTC stopped when Core is halted
61        DBG_RTC_STOP OFFSET(10) NUMBITS(1) [],
62        /// DBG_WWDG_STOP
63        DBG_WWDG_STOP OFFSET(11) NUMBITS(1) [],
64        /// DBG_IWDEG_STOP
65        DBG_IWDEG_STOP OFFSET(12) NUMBITS(1) [],
66        /// DBG_J2C1_SMBUS_TIMEOUT
67        DBG_J2C1_SMBUS_TIMEOUT OFFSET(21) NUMBITS(1) [],
68        /// DBG_J2C2_SMBUS_TIMEOUT
69        DBG_J2C2_SMBUS_TIMEOUT OFFSET(22) NUMBITS(1) [],
70        /// DBG_J2C3SMBUS_TIMEOUT
71        DBG_J2C3SMBUS_TIMEOUT OFFSET(23) NUMBITS(1) [],
72        /// SMBUS timeout mode stopped when Core is halted
73        DBG_I2CFMP_SMBUS_TIMEOUT OFFSET(24) NUMBITS(1) [],
74        /// DBG_CAN1_STOP
75        DBG_CAN1_STOP OFFSET(25) NUMBITS(1) [],
76        /// DBG_CAN2_STOP
77        DBG_CAN2_STOP OFFSET(26) NUMBITS(1) []
78    ],
79    DBGMCU_APB2_FZ [
80        /// TIM1 counter stopped when core is halted
81        DBG_TIM1_STOP OFFSET(0) NUMBITS(1) [],
82        /// TIM8 counter stopped when core is halted
83        DBG_TIM8_STOP OFFSET(1) NUMBITS(1) [],
84        /// TIM9 counter stopped when core is halted
85        DBG_TIM9_STOP OFFSET(16) NUMBITS(1) [],
86        /// TIM10 counter stopped when core is halted
87        DBG_TIM10_STOP OFFSET(17) NUMBITS(1) [],
88        /// TIM11 counter stopped when core is halted
89        DBG_TIM11_STOP OFFSET(18) NUMBITS(1) []
90    ]
91];
92
93const DBG_BASE: StaticRef<DbgRegisters> =
94    unsafe { StaticRef::new(0xE0042000 as *const DbgRegisters) };
95
96pub struct Dbg {
97    registers: StaticRef<DbgRegisters>,
98}
99
100impl Dbg {
101    pub const fn new() -> Dbg {
102        Dbg {
103            registers: DBG_BASE,
104        }
105    }
106
107    pub fn disable_tim2_counter(&self) {
108        self.registers
109            .dbgmcu_apb1_fz
110            .modify(DBGMCU_APB1_FZ::DBG_TIM2_STOP::SET);
111    }
112}
stm32f4xx/dbg.rs

stm32f4xx/
dbg.rs
