lowrisc/registers/
spi_host_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for spi_host.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/spi_host/data/spi_host.hjson
12use kernel::utilities::registers::ReadOnly;
13use kernel::utilities::registers::ReadWrite;
14use kernel::utilities::registers::WriteOnly;
15use kernel::utilities::registers::{register_bitfields, register_structs};
16/// The number of active-low chip select (cs_n) lines to create.
17pub const SPI_HOST_PARAM_NUM_C_S: u32 = 1;
18/// The size of the Tx FIFO (in words)
19pub const SPI_HOST_PARAM_TX_DEPTH: u32 = 72;
20/// The size of the Rx FIFO (in words)
21pub const SPI_HOST_PARAM_RX_DEPTH: u32 = 64;
22/// The size of the Cmd FIFO (one segment descriptor per entry)
23pub const SPI_HOST_PARAM_CMD_DEPTH: u32 = 4;
24/// Number of alerts
25pub const SPI_HOST_PARAM_NUM_ALERTS: u32 = 1;
26/// Register width
27pub const SPI_HOST_PARAM_REG_WIDTH: u32 = 32;
28
29register_structs! {
30    pub SpiHostRegisters {
31        /// Interrupt State Register
32        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
33        /// Interrupt Enable Register
34        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
35        /// Interrupt Test Register
36        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
37        /// Alert Test Register
38        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
39        /// Control register
40        (0x0010 => pub(crate) control: ReadWrite<u32, CONTROL::Register>),
41        /// Status register
42        (0x0014 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
43        /// Configuration options register.
44        (0x0018 => pub(crate) configopts: [ReadWrite<u32, CONFIGOPTS::Register>; 1]),
45        /// Chip-Select ID
46        (0x001c => pub(crate) csid: ReadWrite<u32, CSID::Register>),
47        /// Command Register
48        (0x0020 => pub(crate) command: ReadWrite<u32, COMMAND::Register>),
49        /// Memory area: SPI Receive Data.
50        (0x0024 => pub(crate) rxdata: [ReadOnly<u32>; 1]),
51        /// Memory area: SPI Transmit Data.
52        (0x0028 => pub(crate) txdata: [WriteOnly<u32>; 1]),
53        /// Controls which classes of errors raise an interrupt.
54        (0x002c => pub(crate) error_enable: ReadWrite<u32, ERROR_ENABLE::Register>),
55        /// Indicates that any errors that have occurred.
56        (0x0030 => pub(crate) error_status: ReadWrite<u32, ERROR_STATUS::Register>),
57        /// Controls which classes of SPI events raise an interrupt.
58        (0x0034 => pub(crate) event_enable: ReadWrite<u32, EVENT_ENABLE::Register>),
59        (0x0038 => @END),
60    }
61}
62
63register_bitfields![u32,
64    /// Common Interrupt Offsets
65    pub(crate) INTR [
66        ERROR OFFSET(0) NUMBITS(1) [],
67        SPI_EVENT OFFSET(1) NUMBITS(1) [],
68    ],
69    pub(crate) ALERT_TEST [
70        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
71    ],
72    pub(crate) CONTROL [
73        RX_WATERMARK OFFSET(0) NUMBITS(8) [],
74        TX_WATERMARK OFFSET(8) NUMBITS(8) [],
75        OUTPUT_EN OFFSET(29) NUMBITS(1) [],
76        SW_RST OFFSET(30) NUMBITS(1) [],
77        SPIEN OFFSET(31) NUMBITS(1) [],
78    ],
79    pub(crate) STATUS [
80        TXQD OFFSET(0) NUMBITS(8) [],
81        RXQD OFFSET(8) NUMBITS(8) [],
82        CMDQD OFFSET(16) NUMBITS(4) [],
83        RXWM OFFSET(20) NUMBITS(1) [],
84        BYTEORDER OFFSET(22) NUMBITS(1) [],
85        RXSTALL OFFSET(23) NUMBITS(1) [],
86        RXEMPTY OFFSET(24) NUMBITS(1) [],
87        RXFULL OFFSET(25) NUMBITS(1) [],
88        TXWM OFFSET(26) NUMBITS(1) [],
89        TXSTALL OFFSET(27) NUMBITS(1) [],
90        TXEMPTY OFFSET(28) NUMBITS(1) [],
91        TXFULL OFFSET(29) NUMBITS(1) [],
92        ACTIVE OFFSET(30) NUMBITS(1) [],
93        READY OFFSET(31) NUMBITS(1) [],
94    ],
95    pub(crate) CONFIGOPTS [
96        CLKDIV_0 OFFSET(0) NUMBITS(16) [],
97        CSNIDLE_0 OFFSET(16) NUMBITS(4) [],
98        CSNTRAIL_0 OFFSET(20) NUMBITS(4) [],
99        CSNLEAD_0 OFFSET(24) NUMBITS(4) [],
100        FULLCYC_0 OFFSET(29) NUMBITS(1) [],
101        CPHA_0 OFFSET(30) NUMBITS(1) [],
102        CPOL_0 OFFSET(31) NUMBITS(1) [],
103    ],
104    pub(crate) CSID [
105        CSID OFFSET(0) NUMBITS(32) [],
106    ],
107    pub(crate) COMMAND [
108        LEN OFFSET(0) NUMBITS(9) [],
109        CSAAT OFFSET(9) NUMBITS(1) [],
110        SPEED OFFSET(10) NUMBITS(2) [],
111        DIRECTION OFFSET(12) NUMBITS(2) [],
112    ],
113    pub(crate) ERROR_ENABLE [
114        CMDBUSY OFFSET(0) NUMBITS(1) [],
115        OVERFLOW OFFSET(1) NUMBITS(1) [],
116        UNDERFLOW OFFSET(2) NUMBITS(1) [],
117        CMDINVAL OFFSET(3) NUMBITS(1) [],
118        CSIDINVAL OFFSET(4) NUMBITS(1) [],
119    ],
120    pub(crate) ERROR_STATUS [
121        CMDBUSY OFFSET(0) NUMBITS(1) [],
122        OVERFLOW OFFSET(1) NUMBITS(1) [],
123        UNDERFLOW OFFSET(2) NUMBITS(1) [],
124        CMDINVAL OFFSET(3) NUMBITS(1) [],
125        CSIDINVAL OFFSET(4) NUMBITS(1) [],
126        ACCESSINVAL OFFSET(5) NUMBITS(1) [],
127    ],
128    pub(crate) EVENT_ENABLE [
129        RXFULL OFFSET(0) NUMBITS(1) [],
130        TXEMPTY OFFSET(1) NUMBITS(1) [],
131        RXWM OFFSET(2) NUMBITS(1) [],
132        TXWM OFFSET(3) NUMBITS(1) [],
133        READY OFFSET(4) NUMBITS(1) [],
134        IDLE OFFSET(5) NUMBITS(1) [],
135    ],
136];
137
138// End generated register constants for spi_host
lowrisc/registers/spi_host_regs.rs

lowrisc/registers/
spi_host_regs.rs
