esp32_c3/
sysreg.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! SysReg driver.
6
7use kernel::utilities::registers::interfaces::{ReadWriteable, Readable};
8use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite};
9use kernel::utilities::StaticRef;
10
11pub const SYS_REG_BASE: StaticRef<SysRegRegisters> =
12    unsafe { StaticRef::new(0x600C_0000 as *const SysRegRegisters) };
13
14register_structs! {
15    pub SysRegRegisters {
16        (0x000 => _reserved0),
17        (0x008 => cpu_per_conf: ReadWrite<u32, CPU_PER_CONF::Register>),
18        (0x00c => _reserved1),
19        (0x010 => perip_clk_en0: ReadWrite<u32, PERIP_CLK_EN0::Register>),
20        (0x014 => _reserved3),
21        (0x058 => sysclk_config: ReadWrite<u32, SYSCLK_CONFIG::Register>),
22        (0x05C => _reserved_unimplemented_yet),
23        (0x1000 => @END),
24    }
25}
26
27register_bitfields![u32,
28    PERIP_CLK_EN0 [
29        TIMERGROUP0 OFFSET(13) NUMBITS(1) []
30    ],
31    CPU_PER_CONF [
32        CPUPERIOD_SEL OFFSET(0) NUMBITS(2) [
33            MHz80 = 0,
34            MHz160 = 1,
35        ],
36        PLL_FREQ_SEL OFFSET(2) NUMBITS(1) [
37            MHz320 = 0,
38            MHz480 = 1
39        ],
40        CPU_WAIT_MODE_FORCE_ON OFFSET(3) NUMBITS(1) [],
41        CPU_WAIT_DELAY_NUM OFFSET(4) NUMBITS(4) [],
42    ],
43    SYSCLK_CONFIG [
44        PRE_DIV_CNT OFFSET(0) NUMBITS(10) [],
45        SOC_CLK_SEL OFFSET(10) NUMBITS(2) [
46            Xtal = 0,
47            Pll = 1,
48            Fosc = 2
49        ],
50        CLK_XTAL_FREQ OFFSET(12) NUMBITS(6) [],
51    ]
52];
53
54#[repr(u32)]
55pub enum PllFrequency {
56    MHz320 = 0,
57    MHz480 = 1,
58}
59
60#[repr(u32)]
61pub enum CpuFrequency {
62    MHz80 = 0,
63    MHz160 = 1,
64}
65
66pub struct SysReg {
67    registers: StaticRef<SysRegRegisters>,
68}
69
70impl SysReg {
71    pub const fn new() -> Self {
72        SysReg {
73            registers: SYS_REG_BASE,
74        }
75    }
76
77    pub fn use_xtal_clock_source(&self) {
78        self.registers
79            .sysclk_config
80            .modify(SYSCLK_CONFIG::SOC_CLK_SEL::Xtal);
81    }
82
83    pub fn use_pll_clock_source(&self, pll_frequency: PllFrequency, cpu_frequency: CpuFrequency) {
84        self.registers
85            .sysclk_config
86            .modify(SYSCLK_CONFIG::SOC_CLK_SEL::Pll);
87        self.registers.cpu_per_conf.modify(
88            CPU_PER_CONF::PLL_FREQ_SEL.val(pll_frequency as u32)
89                + CPU_PER_CONF::CPUPERIOD_SEL.val(cpu_frequency as u32),
90        );
91    }
92
93    pub fn enable_timg0(&self) {
94        self.registers
95            .perip_clk_en0
96            .modify(PERIP_CLK_EN0::TIMERGROUP0::SET);
97    }
98
99    pub fn disable_timg0(&self) {
100        self.registers
101            .perip_clk_en0
102            .modify(PERIP_CLK_EN0::TIMERGROUP0::CLEAR);
103    }
104
105    pub fn is_enabled_timg0(&self) -> bool {
106        self.registers
107            .perip_clk_en0
108            .is_set(PERIP_CLK_EN0::TIMERGROUP0)
109    }
110}
esp32_c3/sysreg.rs

esp32_c3/
sysreg.rs
