lowrisc/registers/
pwm_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for pwm.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/pwm/data/pwm.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of PWM outputs
15pub const PWM_PARAM_N_OUTPUTS: u32 = 6;
16/// Number of alerts
17pub const PWM_PARAM_NUM_ALERTS: u32 = 1;
18/// Register width
19pub const PWM_PARAM_REG_WIDTH: u32 = 32;
20
21register_structs! {
22    pub PwmRegisters {
23        /// Alert Test Register
24        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
25        /// Register write enable for all control registers
26        (0x0004 => pub(crate) regwen: ReadWrite<u32, REGWEN::Register>),
27        /// Configuration register
28        (0x0008 => pub(crate) cfg: ReadWrite<u32, CFG::Register>),
29        /// Enable PWM operation for each channel
30        (0x000c => pub(crate) pwm_en: [ReadWrite<u32, PWM_EN::Register>; 1]),
31        /// Invert the PWM output for each channel
32        (0x0010 => pub(crate) invert: [ReadWrite<u32, INVERT::Register>; 1]),
33        /// Basic PWM Channel Parameters
34        (0x0014 => pub(crate) pwm_param: [ReadWrite<u32, PWM_PARAM::Register>; 6]),
35        /// Controls the duty_cycle of each channel.
36        (0x002c => pub(crate) duty_cycle: [ReadWrite<u32, DUTY_CYCLE::Register>; 6]),
37        /// Hardware controlled blink/heartbeat parameters.
38        (0x0044 => pub(crate) blink_param: [ReadWrite<u32, BLINK_PARAM::Register>; 6]),
39        (0x005c => @END),
40    }
41}
42
43register_bitfields![u32,
44    pub(crate) ALERT_TEST [
45        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
46    ],
47    pub(crate) REGWEN [
48        REGWEN OFFSET(0) NUMBITS(1) [],
49    ],
50    pub(crate) CFG [
51        CLK_DIV OFFSET(0) NUMBITS(27) [],
52        DC_RESN OFFSET(27) NUMBITS(4) [],
53        CNTR_EN OFFSET(31) NUMBITS(1) [],
54    ],
55    pub(crate) PWM_EN [
56        EN_0 OFFSET(0) NUMBITS(1) [],
57        EN_1 OFFSET(1) NUMBITS(1) [],
58        EN_2 OFFSET(2) NUMBITS(1) [],
59        EN_3 OFFSET(3) NUMBITS(1) [],
60        EN_4 OFFSET(4) NUMBITS(1) [],
61        EN_5 OFFSET(5) NUMBITS(1) [],
62    ],
63    pub(crate) INVERT [
64        INVERT_0 OFFSET(0) NUMBITS(1) [],
65        INVERT_1 OFFSET(1) NUMBITS(1) [],
66        INVERT_2 OFFSET(2) NUMBITS(1) [],
67        INVERT_3 OFFSET(3) NUMBITS(1) [],
68        INVERT_4 OFFSET(4) NUMBITS(1) [],
69        INVERT_5 OFFSET(5) NUMBITS(1) [],
70    ],
71    pub(crate) PWM_PARAM [
72        PHASE_DELAY_0 OFFSET(0) NUMBITS(16) [],
73        HTBT_EN_0 OFFSET(30) NUMBITS(1) [],
74        BLINK_EN_0 OFFSET(31) NUMBITS(1) [],
75    ],
76    pub(crate) DUTY_CYCLE [
77        A_0 OFFSET(0) NUMBITS(16) [],
78        B_0 OFFSET(16) NUMBITS(16) [],
79    ],
80    pub(crate) BLINK_PARAM [
81        X_0 OFFSET(0) NUMBITS(16) [],
82        Y_0 OFFSET(16) NUMBITS(16) [],
83    ],
84];
85
86// End generated register constants for pwm
lowrisc/registers/pwm_regs.rs

lowrisc/registers/
pwm_regs.rs
