riscv/csr/
mip.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use kernel::utilities::registers::register_bitfields;
6
7register_bitfields![usize,
8    pub mip [
9        usoft OFFSET(0) NUMBITS(1) [],
10        ssoft OFFSET(1) NUMBITS(1) [],
11        msoft OFFSET(3) NUMBITS(1) [],
12        utimer OFFSET(4) NUMBITS(1) [],
13        stimer OFFSET(5) NUMBITS(1) [],
14        mtimer OFFSET(7) NUMBITS(1) [],
15        uext OFFSET(8) NUMBITS(1) [],
16        sext OFFSET(9) NUMBITS(1) [],
17        mext OFFSET(11) NUMBITS(1) [],
18        BIT16 OFFSET(16) NUMBITS(1) [],
19        BIT17 OFFSET(17) NUMBITS(1) [],
20        BIT18 OFFSET(18) NUMBITS(1) [],
21        BIT19 OFFSET(19) NUMBITS(1) [],
22        BIT20 OFFSET(20) NUMBITS(1) [],
23        BIT21 OFFSET(21) NUMBITS(1) [],
24        BIT22 OFFSET(22) NUMBITS(1) [],
25        BIT23 OFFSET(23) NUMBITS(1) [],
26        BIT24 OFFSET(24) NUMBITS(1) [],
27        BIT25 OFFSET(25) NUMBITS(1) [],
28        BIT26 OFFSET(26) NUMBITS(1) [],
29        BIT27 OFFSET(27) NUMBITS(1) [],
30        BIT28 OFFSET(28) NUMBITS(1) [],
31        BIT29 OFFSET(29) NUMBITS(1) [],
32        BIT30 OFFSET(30) NUMBITS(1) [],
33        BIT31 OFFSET(31) NUMBITS(1) [],
34    ]
35];
riscv/csr/mip.rs

riscv/csr/
mip.rs
