lowrisc/registers/
hmac_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for hmac.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/hmac/data/hmac.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::WriteOnly;
14use kernel::utilities::registers::{register_bitfields, register_structs};
15/// Number of words for digest/ key
16pub const HMAC_PARAM_NUM_WORDS: u32 = 8;
17/// Number of alerts
18pub const HMAC_PARAM_NUM_ALERTS: u32 = 1;
19/// Register width
20pub const HMAC_PARAM_REG_WIDTH: u32 = 32;
21
22register_structs! {
23    pub HmacRegisters {
24        /// Interrupt State Register
25        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
26        /// Interrupt Enable Register
27        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
28        /// Interrupt Test Register
29        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
30        /// Alert Test Register
31        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
32        /// HMAC Configuration register.
33        (0x0010 => pub(crate) cfg: ReadWrite<u32, CFG::Register>),
34        /// HMAC command register
35        (0x0014 => pub(crate) cmd: ReadWrite<u32, CMD::Register>),
36        /// HMAC Status register
37        (0x0018 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
38        /// HMAC Error Code
39        (0x001c => pub(crate) err_code: ReadWrite<u32, ERR_CODE::Register>),
40        /// Randomize internal secret registers.
41        (0x0020 => pub(crate) wipe_secret: ReadWrite<u32, WIPE_SECRET::Register>),
42        /// HMAC Secret Key
43        (0x0024 => pub(crate) key: [ReadWrite<u32, KEY::Register>; 8]),
44        /// Digest output. If HMAC is disabled, the register shows result of SHA256
45        (0x0044 => pub(crate) digest: [ReadWrite<u32, DIGEST::Register>; 8]),
46        /// Received Message Length calculated by the HMAC in bits [31:0]
47        (0x0064 => pub(crate) msg_length_lower: ReadWrite<u32, MSG_LENGTH_LOWER::Register>),
48        /// Received Message Length calculated by the HMAC in bits [63:32]
49        (0x0068 => pub(crate) msg_length_upper: ReadWrite<u32, MSG_LENGTH_UPPER::Register>),
50        (0x006c => _reserved1),
51        /// Memory area: Message FIFO. Any write to this window will be appended to the FIFO. Only the
52        /// lower [1:0] bits of the address matter to writes within the window (for correctly dealing
53        /// with non 32-bit writes)
54        (0x0800 => pub(crate) msg_fifo: [WriteOnly<u32>; 512]),
55        (0x1000 => @END),
56    }
57}
58
59register_bitfields![u32,
60    /// Common Interrupt Offsets
61    pub(crate) INTR [
62        HMAC_DONE OFFSET(0) NUMBITS(1) [],
63        FIFO_EMPTY OFFSET(1) NUMBITS(1) [],
64        HMAC_ERR OFFSET(2) NUMBITS(1) [],
65    ],
66    pub(crate) ALERT_TEST [
67        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
68    ],
69    pub(crate) CFG [
70        HMAC_EN OFFSET(0) NUMBITS(1) [],
71        SHA_EN OFFSET(1) NUMBITS(1) [],
72        ENDIAN_SWAP OFFSET(2) NUMBITS(1) [],
73        DIGEST_SWAP OFFSET(3) NUMBITS(1) [],
74    ],
75    pub(crate) CMD [
76        HASH_START OFFSET(0) NUMBITS(1) [],
77        HASH_PROCESS OFFSET(1) NUMBITS(1) [],
78    ],
79    pub(crate) STATUS [
80        FIFO_EMPTY OFFSET(0) NUMBITS(1) [],
81        FIFO_FULL OFFSET(1) NUMBITS(1) [],
82        FIFO_DEPTH OFFSET(4) NUMBITS(5) [],
83    ],
84    pub(crate) ERR_CODE [
85        ERR_CODE OFFSET(0) NUMBITS(32) [],
86    ],
87    pub(crate) WIPE_SECRET [
88        SECRET OFFSET(0) NUMBITS(32) [],
89    ],
90    pub(crate) KEY [
91        KEY_0 OFFSET(0) NUMBITS(32) [],
92    ],
93    pub(crate) DIGEST [
94        DIGEST_0 OFFSET(0) NUMBITS(32) [],
95    ],
96    pub(crate) MSG_LENGTH_LOWER [
97        V OFFSET(0) NUMBITS(32) [],
98    ],
99    pub(crate) MSG_LENGTH_UPPER [
100        V OFFSET(0) NUMBITS(32) [],
101    ],
102];
103
104// End generated register constants for hmac
lowrisc/registers/hmac_regs.rs

lowrisc/registers/
hmac_regs.rs
