lowrisc/registers/
aon_timer_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for aon_timer.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/aon_timer/data/aon_timer.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const AON_TIMER_PARAM_NUM_ALERTS: u32 = 1;
16/// Register width
17pub const AON_TIMER_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub AonTimerRegisters {
21        /// Alert Test Register
22        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
23        /// Wakeup Timer Control register
24        (0x0004 => pub(crate) wkup_ctrl: ReadWrite<u32, WKUP_CTRL::Register>),
25        /// Wakeup Timer Threshold Register
26        (0x0008 => pub(crate) wkup_thold: ReadWrite<u32, WKUP_THOLD::Register>),
27        /// Wakeup Timer Count Register
28        (0x000c => pub(crate) wkup_count: ReadWrite<u32, WKUP_COUNT::Register>),
29        /// Watchdog Timer Write Enable Register
30        (0x0010 => pub(crate) wdog_regwen: ReadWrite<u32, WDOG_REGWEN::Register>),
31        /// Watchdog Timer Control register
32        (0x0014 => pub(crate) wdog_ctrl: ReadWrite<u32, WDOG_CTRL::Register>),
33        /// Watchdog Timer Bark Threshold Register
34        (0x0018 => pub(crate) wdog_bark_thold: ReadWrite<u32, WDOG_BARK_THOLD::Register>),
35        /// Watchdog Timer Bite Threshold Register
36        (0x001c => pub(crate) wdog_bite_thold: ReadWrite<u32, WDOG_BITE_THOLD::Register>),
37        /// Watchdog Timer Count Register
38        (0x0020 => pub(crate) wdog_count: ReadWrite<u32, WDOG_COUNT::Register>),
39        /// Interrupt State Register
40        (0x0024 => pub(crate) intr_state: ReadWrite<u32, INTR_STATE::Register>),
41        /// Interrupt Test Register
42        (0x0028 => pub(crate) intr_test: ReadWrite<u32, INTR_TEST::Register>),
43        /// Wakeup request status
44        (0x002c => pub(crate) wkup_cause: ReadWrite<u32, WKUP_CAUSE::Register>),
45        (0x0030 => @END),
46    }
47}
48
49register_bitfields![u32,
50    pub(crate) ALERT_TEST [
51        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
52    ],
53    pub(crate) WKUP_CTRL [
54        ENABLE OFFSET(0) NUMBITS(1) [],
55        PRESCALER OFFSET(1) NUMBITS(12) [],
56    ],
57    pub(crate) WKUP_THOLD [
58        THRESHOLD OFFSET(0) NUMBITS(32) [],
59    ],
60    pub(crate) WKUP_COUNT [
61        COUNT OFFSET(0) NUMBITS(32) [],
62    ],
63    pub(crate) WDOG_REGWEN [
64        REGWEN OFFSET(0) NUMBITS(1) [],
65    ],
66    pub(crate) WDOG_CTRL [
67        ENABLE OFFSET(0) NUMBITS(1) [],
68        PAUSE_IN_SLEEP OFFSET(1) NUMBITS(1) [],
69    ],
70    pub(crate) WDOG_BARK_THOLD [
71        THRESHOLD OFFSET(0) NUMBITS(32) [],
72    ],
73    pub(crate) WDOG_BITE_THOLD [
74        THRESHOLD OFFSET(0) NUMBITS(32) [],
75    ],
76    pub(crate) WDOG_COUNT [
77        COUNT OFFSET(0) NUMBITS(32) [],
78    ],
79    pub(crate) INTR_STATE [
80        WKUP_TIMER_EXPIRED OFFSET(0) NUMBITS(1) [],
81        WDOG_TIMER_BARK OFFSET(1) NUMBITS(1) [],
82    ],
83    pub(crate) INTR_TEST [
84        WKUP_TIMER_EXPIRED OFFSET(0) NUMBITS(1) [],
85        WDOG_TIMER_BARK OFFSET(1) NUMBITS(1) [],
86    ],
87    pub(crate) WKUP_CAUSE [
88        CAUSE OFFSET(0) NUMBITS(1) [],
89    ],
90];
91
92// End generated register constants for aon_timer
lowrisc/registers/aon_timer_regs.rs

lowrisc/registers/
aon_timer_regs.rs
