lowrisc/registers/
adc_ctrl_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for adc_ctrl.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/adc_ctrl/data/adc_ctrl.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number for ADC filters
15pub const ADC_CTRL_PARAM_NUM_ADC_FILTER: u32 = 8;
16/// Number for ADC channels
17pub const ADC_CTRL_PARAM_NUM_ADC_CHANNEL: u32 = 2;
18/// Number of alerts
19pub const ADC_CTRL_PARAM_NUM_ALERTS: u32 = 1;
20/// Register width
21pub const ADC_CTRL_PARAM_REG_WIDTH: u32 = 32;
22
23register_structs! {
24    pub AdcCtrlRegisters {
25        /// Interrupt State Register
26        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
27        /// Interrupt Enable Register
28        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
29        /// Interrupt Test Register
30        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
31        /// Alert Test Register
32        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
33        /// ADC enable control register
34        (0x0010 => pub(crate) adc_en_ctl: ReadWrite<u32, ADC_EN_CTL::Register>),
35        /// ADC PowerDown(PD) control register
36        (0x0014 => pub(crate) adc_pd_ctl: ReadWrite<u32, ADC_PD_CTL::Register>),
37        /// ADC Low-Power(LP) sample control register
38        (0x0018 => pub(crate) adc_lp_sample_ctl: ReadWrite<u32, ADC_LP_SAMPLE_CTL::Register>),
39        /// ADC sample control register
40        (0x001c => pub(crate) adc_sample_ctl: ReadWrite<u32, ADC_SAMPLE_CTL::Register>),
41        /// ADC FSM reset control
42        (0x0020 => pub(crate) adc_fsm_rst: ReadWrite<u32, ADC_FSM_RST::Register>),
43        /// ADC channel0 filter range
44        (0x0024 => pub(crate) adc_chn0_filter_ctl: [ReadWrite<u32, ADC_CHN0_FILTER_CTL::Register>; 8]),
45        /// ADC channel1 filter range
46        (0x0044 => pub(crate) adc_chn1_filter_ctl: [ReadWrite<u32, ADC_CHN1_FILTER_CTL::Register>; 8]),
47        /// ADC value sampled on channel
48        (0x0064 => pub(crate) adc_chn_val: [ReadWrite<u32, ADC_CHN_VAL::Register>; 2]),
49        /// Enable filter matches as wakeups
50        (0x006c => pub(crate) adc_wakeup_ctl: ReadWrite<u32, ADC_WAKEUP_CTL::Register>),
51        /// Adc filter match status
52        (0x0070 => pub(crate) filter_status: ReadWrite<u32, FILTER_STATUS::Register>),
53        /// Interrupt enable controls.
54        (0x0074 => pub(crate) adc_intr_ctl: ReadWrite<u32, ADC_INTR_CTL::Register>),
55        /// Debug cable internal status
56        (0x0078 => pub(crate) adc_intr_status: ReadWrite<u32, ADC_INTR_STATUS::Register>),
57        (0x007c => @END),
58    }
59}
60
61register_bitfields![u32,
62    /// Common Interrupt Offsets
63    pub(crate) INTR [
64        MATCH_DONE OFFSET(0) NUMBITS(1) [],
65    ],
66    pub(crate) ALERT_TEST [
67        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
68    ],
69    pub(crate) ADC_EN_CTL [
70        ADC_ENABLE OFFSET(0) NUMBITS(1) [],
71        ONESHOT_MODE OFFSET(1) NUMBITS(1) [],
72    ],
73    pub(crate) ADC_PD_CTL [
74        LP_MODE OFFSET(0) NUMBITS(1) [],
75        PWRUP_TIME OFFSET(4) NUMBITS(4) [],
76        WAKEUP_TIME OFFSET(8) NUMBITS(24) [],
77    ],
78    pub(crate) ADC_LP_SAMPLE_CTL [
79        LP_SAMPLE_CNT OFFSET(0) NUMBITS(8) [],
80    ],
81    pub(crate) ADC_SAMPLE_CTL [
82        NP_SAMPLE_CNT OFFSET(0) NUMBITS(16) [],
83    ],
84    pub(crate) ADC_FSM_RST [
85        RST_EN OFFSET(0) NUMBITS(1) [],
86    ],
87    pub(crate) ADC_CHN0_FILTER_CTL [
88        MIN_V_0 OFFSET(2) NUMBITS(10) [],
89        COND_0 OFFSET(12) NUMBITS(1) [],
90        MAX_V_0 OFFSET(18) NUMBITS(10) [],
91        EN_0 OFFSET(31) NUMBITS(1) [],
92    ],
93    pub(crate) ADC_CHN1_FILTER_CTL [
94        MIN_V_0 OFFSET(2) NUMBITS(10) [],
95        COND_0 OFFSET(12) NUMBITS(1) [],
96        MAX_V_0 OFFSET(18) NUMBITS(10) [],
97        EN_0 OFFSET(31) NUMBITS(1) [],
98    ],
99    pub(crate) ADC_CHN_VAL [
100        ADC_CHN_VALUE_EXT_0 OFFSET(0) NUMBITS(2) [],
101        ADC_CHN_VALUE_0 OFFSET(2) NUMBITS(10) [],
102        ADC_CHN_VALUE_INTR_EXT_0 OFFSET(16) NUMBITS(2) [],
103        ADC_CHN_VALUE_INTR_0 OFFSET(18) NUMBITS(10) [],
104    ],
105    pub(crate) ADC_WAKEUP_CTL [
106        EN OFFSET(0) NUMBITS(8) [],
107    ],
108    pub(crate) FILTER_STATUS [
109        COND OFFSET(0) NUMBITS(8) [],
110    ],
111    pub(crate) ADC_INTR_CTL [
112        EN OFFSET(0) NUMBITS(9) [],
113    ],
114    pub(crate) ADC_INTR_STATUS [
115        FILTER_MATCH OFFSET(0) NUMBITS(8) [],
116        ONESHOT OFFSET(8) NUMBITS(1) [],
117    ],
118];
119
120// End generated register constants for adc_ctrl
lowrisc/registers/adc_ctrl_regs.rs

lowrisc/registers/
adc_ctrl_regs.rs
