riscv/csr/
mie.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use kernel::utilities::registers::register_bitfields;
6
7// mtvec contains the address(es) of the trap handler
8register_bitfields![usize,
9    pub mie [
10        usoft OFFSET(0) NUMBITS(1) [],
11        ssoft OFFSET(1) NUMBITS(1) [],
12        msoft OFFSET(3) NUMBITS(1) [],
13        utimer OFFSET(4) NUMBITS(1) [],
14        stimer OFFSET(5) NUMBITS(1) [],
15        mtimer OFFSET(7) NUMBITS(1) [],
16        uext OFFSET(8) NUMBITS(1) [],
17        sext OFFSET(9) NUMBITS(1) [],
18        mext OFFSET(11) NUMBITS(1) [],
19        BIT16 OFFSET(16) NUMBITS(1) [],
20        BIT17 OFFSET(17) NUMBITS(1) [],
21        BIT18 OFFSET(18) NUMBITS(1) [],
22        BIT19 OFFSET(19) NUMBITS(1) [],
23        BIT20 OFFSET(20) NUMBITS(1) [],
24        BIT21 OFFSET(21) NUMBITS(1) [],
25        BIT22 OFFSET(22) NUMBITS(1) [],
26        BIT23 OFFSET(23) NUMBITS(1) [],
27        BIT24 OFFSET(24) NUMBITS(1) [],
28        BIT25 OFFSET(25) NUMBITS(1) [],
29        BIT26 OFFSET(26) NUMBITS(1) [],
30        BIT27 OFFSET(27) NUMBITS(1) [],
31        BIT28 OFFSET(28) NUMBITS(1) [],
32        BIT29 OFFSET(29) NUMBITS(1) [],
33        BIT30 OFFSET(30) NUMBITS(1) [],
34        BIT31 OFFSET(31) NUMBITS(1) [],
35    ]
36];