1use crate::clocks::{phclk, Stm32f4Clocks};
12use core::cell::Cell;
13use kernel::deferred_call::{DeferredCall, DeferredCallClient};
14use kernel::hil::can::{self, StandardBitTiming};
15use kernel::platform::chip::ClockInterface;
16use kernel::utilities::cells::{OptionalCell, TakeCell};
17use kernel::utilities::registers::interfaces::{ReadWriteable, Readable};
18use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite};
19use kernel::utilities::StaticRef;
20
21pub const BRP_MIN_STM32: u32 = 0;
22pub const BRP_MAX_STM32: u32 = 1023;
23
24pub const TX_MAILBOX_COUNT: usize = 3;
25pub const RX_MAILBOX_COUNT: usize = 2;
26pub const FILTER_COUNT: usize = 56;
27
28register_structs! {
29 pub Registers {
30 (0x000 => can_mcr: ReadWrite<u32, CAN_MCR::Register>),
32 (0x004 => can_msr: ReadWrite<u32, CAN_MSR::Register>),
34 (0x008 => can_tsr: ReadWrite<u32, CAN_TSR::Register>),
36 (0x00c => can_rf0r: ReadWrite<u32, CAN_RF0R::Register>),
38 (0x010 => can_rf1r: ReadWrite<u32, CAN_RF1R::Register>),
40 (0x014 => can_ier: ReadWrite<u32, CAN_IER::Register>),
42 (0x018 => can_esr: ReadWrite<u32, CAN_ESR::Register>),
44 (0x01c => can_btr: ReadWrite<u32, CAN_BTR::Register>),
46 (0x020 => _reserved0),
47 (0x180 => can_tx_mailbox: [TransmitMailBox; TX_MAILBOX_COUNT]),
53 (0x1b0 => can_rx_mailbox: [ReceiveMailBox; RX_MAILBOX_COUNT]),
55 (0x1d0 => _reserved1),
56 (0x200 => can_fmr: ReadWrite<u32, CAN_FMR::Register>),
63 (0x204 => can_fm1r: ReadWrite<u32, CAN_FM1R::Register>),
65 (0x208 => _reserved2),
66 (0x20c => can_fs1r: ReadWrite<u32, CAN_FS1R::Register>),
68 (0x210 => _reserved3),
69 (0x214 => can_ffa1r: ReadWrite<u32, CAN_FFA1R::Register>),
71 (0x218 => _reserved4),
72 (0x21c => can_fa1r: ReadWrite<u32, CAN_FA1R::Register>),
74 (0x220 => _reserved5),
75 (0x240 => can_firx: [ReadWrite<u32, CAN_FiRx::Register>; FILTER_COUNT]),
77 (0x320 => @END),
78 },
79
80 TransmitMailBox {
81 (0x00 => can_tir: ReadWrite<u32, CAN_TIxR::Register>),
82 (0x04 => can_tdtr: ReadWrite<u32, CAN_TDTxR::Register>),
83 (0x08 => can_tdlr: ReadWrite<u32, CAN_TDLxR::Register>),
84 (0x0c => can_tdhr: ReadWrite<u32, CAN_TDHxR::Register>),
85 (0x010 => @END),
86 },
87
88 ReceiveMailBox {
89 (0x00 => can_rir: ReadWrite<u32, CAN_RIxR::Register>),
90 (0x04 => can_rdtr: ReadWrite<u32, CAN_RDTxR::Register>),
91 (0x08 => can_rdlr: ReadWrite<u32, CAN_RDLxR::Register>),
92 (0x0c => can_rdhr: ReadWrite<u32, CAN_RDHxR::Register>),
93 (0x010 => @END),
94 }
95}
96
97register_bitfields![u32,
98 CAN_MCR [
99 DBF OFFSET(16) NUMBITS(1) [],
101 RESET OFFSET(15) NUMBITS(1) [],
103 TTCM OFFSET(7) NUMBITS(1) [],
105 ABOM OFFSET(6) NUMBITS(1) [],
107 AWUM OFFSET(5) NUMBITS(1) [],
109 NART OFFSET(4) NUMBITS(1) [],
111 RFLM OFFSET(3) NUMBITS(1) [],
113 TXFP OFFSET(2) NUMBITS(1) [],
115 SLEEP OFFSET(1) NUMBITS(1) [],
117 INRQ OFFSET(0) NUMBITS(1) []
119 ],
120 CAN_MSR [
121 RX OFFSET(11) NUMBITS(1) [],
123 SAMP OFFSET(10) NUMBITS(1) [],
125 RXM OFFSET(9) NUMBITS(1) [],
127 TXM OFFSET(8) NUMBITS(1) [],
129 SLAKI OFFSET(4) NUMBITS(1) [],
131 WKUI OFFSET(3) NUMBITS(1) [],
133 ERRI OFFSET(2) NUMBITS(1) [],
135 SLAK OFFSET(1) NUMBITS(1) [],
137 INAK OFFSET(0) NUMBITS(1) []
139 ],
140 CAN_TSR [
141 LOW2 OFFSET(31) NUMBITS(1) [],
143 LOW1 OFFSET(30) NUMBITS(1) [],
145 LOW0 OFFSET(29) NUMBITS(1) [],
147 TME2 OFFSET(28) NUMBITS(1) [],
149 TME1 OFFSET(27) NUMBITS(1) [],
151 TME0 OFFSET(26) NUMBITS(1) [],
153 CODE OFFSET(24) NUMBITS(2) [],
155 ABRQ2 OFFSET(23) NUMBITS(1) [],
157 TERR2 OFFSET(19) NUMBITS(1) [],
159 ALST2 OFFSET(18) NUMBITS(1) [],
161 TXOK2 OFFSET(17) NUMBITS(1) [],
163 RQCP2 OFFSET(16) NUMBITS(1) [],
165 ABRQ1 OFFSET(15) NUMBITS(1) [],
167 TERR1 OFFSET(11) NUMBITS(1) [],
169 ALST1 OFFSET(10) NUMBITS(1) [],
171 TXOK1 OFFSET(9) NUMBITS(1) [],
173 RQCP1 OFFSET(8) NUMBITS(1) [],
175 ABRQ0 OFFSET(7) NUMBITS(1) [],
177 TERR0 OFFSET(3) NUMBITS(1) [],
179 ALST0 OFFSET(2) NUMBITS(1) [],
181 TXOK0 OFFSET(1) NUMBITS(1) [],
183 RQCP0 OFFSET(0) NUMBITS(1) []
185 ],
186 CAN_RF0R [
187 RFOM0 OFFSET(5) NUMBITS(1) [],
189 FOVR0 OFFSET(4) NUMBITS(1) [],
191 FULL0 OFFSET(3) NUMBITS(1) [],
193 FMP0 OFFSET(0) NUMBITS(2) []
195 ],
196 CAN_RF1R [
197 RFOM1 OFFSET(5) NUMBITS(1) [],
199 FOVR1 OFFSET(4) NUMBITS(1) [],
201 FULL1 OFFSET(3) NUMBITS(1) [],
203 FMP1 OFFSET(0) NUMBITS(2) []
205 ],
206 CAN_IER [
207 SLKIE OFFSET(17) NUMBITS(1) [],
209 WKUIE OFFSET(16) NUMBITS(1) [],
211 ERRIE OFFSET(15) NUMBITS(1) [],
213 LECIE OFFSET(11) NUMBITS(1) [],
215 BOFIE OFFSET(10) NUMBITS(1) [],
217 EPVIE OFFSET(9) NUMBITS(1) [],
219 EWGIE OFFSET(8) NUMBITS(1) [],
221 FOVIE1 OFFSET(6) NUMBITS(1) [],
223 FFIE1 OFFSET(5) NUMBITS(1) [],
225 FMPIE1 OFFSET(4) NUMBITS(1) [],
227 FOVIE0 OFFSET(3) NUMBITS(1) [],
229 FFIE0 OFFSET(2) NUMBITS(1) [],
231 FMPIE0 OFFSET(1) NUMBITS(1) [],
233 TMEIE OFFSET(0) NUMBITS(1) []
235 ],
236 CAN_ESR [
237 REC OFFSET(24) NUMBITS(8) [],
239 TEC OFFSET(16) NUMBITS(8) [],
241 LEC OFFSET(4) NUMBITS(3) [
243 NoError = 0,
244 StuffError = 1,
245 FormError = 2,
246 AcknowledgmentError = 3,
247 BitRecessiveError = 4,
248 BitDominantError = 5,
249 CrcError = 6,
250 SetBySoftware = 7
251 ],
252 BOFF OFFSET(2) NUMBITS(1) [],
254 EPVF OFFSET(1) NUMBITS(1) [],
256 EWGF OFFSET(0) NUMBITS(1) []
258 ],
259 CAN_BTR [
260 SILM OFFSET(31) NUMBITS(1) [],
262 LBKM OFFSET(30) NUMBITS(1) [],
264 SJW OFFSET(24) NUMBITS(2) [],
266 TS2 OFFSET(20) NUMBITS(3) [],
268 TS1 OFFSET(16) NUMBITS(4) [],
270 BRP OFFSET(0) NUMBITS(10) []
272 ],
273 CAN_TIxR [
279 STID OFFSET(21) NUMBITS(11) [],
281 EXID OFFSET(3) NUMBITS(18) [],
283 IDE OFFSET(2) NUMBITS(1) [],
285 RTR OFFSET(1) NUMBITS(1) [],
287 TXRQ OFFSET(0) NUMBITS(1) []
289 ],
290 CAN_TDTxR [
291 TIME OFFSET(16) NUMBITS(16) [],
293 TGT OFFSET(8) NUMBITS(1) [],
295 DLC OFFSET(0) NUMBITS(4) []
297 ],
298 CAN_TDLxR [
299 DATA3 OFFSET(24) NUMBITS(8) [],
301 DATA2 OFFSET(16) NUMBITS(8) [],
303 DATA1 OFFSET(8) NUMBITS(8) [],
305 DATA0 OFFSET(0) NUMBITS(8) []
307 ],
308 CAN_TDHxR [
309 DATA7 OFFSET(24) NUMBITS(8) [],
311 DATA6 OFFSET(16) NUMBITS(8) [],
313 DATA5 OFFSET(8) NUMBITS(8) [],
315 DATA4 OFFSET(0) NUMBITS(8) []
317 ],
318 CAN_RIxR [
319 STID OFFSET(21) NUMBITS(11) [],
321 EXID OFFSET(3) NUMBITS(18) [],
323 IDE OFFSET(2) NUMBITS(1) [],
325 RTR OFFSET(1) NUMBITS(1) []
327 ],
328 CAN_RDTxR [
329 TIME OFFSET(16) NUMBITS(16) [],
331 FMI OFFSET(8) NUMBITS(8) [],
333 DLC OFFSET(0) NUMBITS(4) []
335 ],
336 CAN_RDLxR [
337 DATA3 OFFSET(24) NUMBITS(8) [],
339 DATA2 OFFSET(16) NUMBITS(8) [],
341 DATA1 OFFSET(8) NUMBITS(8) [],
343 DATA0 OFFSET(0) NUMBITS(8) []
345 ],
346 CAN_RDHxR [
347 DATA7 OFFSET(24) NUMBITS(8) [],
349 DATA6 OFFSET(16) NUMBITS(8) [],
351 DATA5 OFFSET(8) NUMBITS(8) [],
353 DATA4 OFFSET(0) NUMBITS(8) []
355 ],
356 CAN_FMR [
362 CANSB OFFSET(8) NUMBITS(6) [],
364 FINIT OFFSET(0) NUMBITS(1) []
366 ],
367 CAN_FM1R [
369 FBM OFFSET(0) NUMBITS(28) []
371 ],
372 CAN_FS1R [
373 FSC OFFSET(0) NUMBITS(28) []
375 ],
376 CAN_FFA1R [
377 FFA OFFSET(0) NUMBITS(28) []
379 ],
380 CAN_FA1R [
381 FACT OFFSET(0) NUMBITS(28) []
383 ],
384 CAN_FiRx [
385 FB OFFSET(0) NUMBITS(32) []
387 ]
388];
389
390#[derive(Copy, Clone, PartialEq)]
391enum CanState {
392 Initialization,
393 Normal,
394 Sleep,
395 RunningError(can::Error),
396}
397
398#[derive(Copy, Clone, PartialEq)]
400enum AsyncAction {
401 Enable,
402 AbortReceive,
403 Disabled,
404 EnableError(kernel::ErrorCode),
405}
406
407#[repr(u32)]
408enum BitSegment1 {
409 CanBtrTs1Min = 0b0000,
410 CanBtrTs1Max = 0b1111,
411}
412
413#[repr(u32)]
414enum BitSegment2 {
415 CanBtrTs2Min = 0b0000,
416 CanBtrTs2Max = 0b0111,
417}
418
419#[repr(u32)]
420enum SynchronizationJumpWidth {
421 CanBtrSjwMin = 0b00,
422 CanBtrSjwMax = 0b11,
423}
424
425#[derive(Copy, Clone, PartialEq)]
426pub enum CanInterruptMode {
427 TransmitInterrupt,
428 Fifo0Interrupt,
429 Fifo1Interrupt,
430 ErrorAndStatusChangeInterrupt,
431}
432
433impl From<CanState> for can::State {
434 fn from(state: CanState) -> Self {
435 match state {
436 CanState::Initialization | CanState::Sleep => can::State::Disabled,
437 CanState::Normal => can::State::Running,
438 CanState::RunningError(err) => can::State::Error(err),
439 }
440 }
441}
442
443pub struct Can<'a> {
444 registers: StaticRef<Registers>,
445 clock: CanClock<'a>,
446 can_state: Cell<CanState>,
447 error_interrupt_counter: Cell<u32>,
448 fifo0_interrupt_counter: Cell<u32>,
449 fifo1_interrupt_counter: Cell<u32>,
450 failed_messages: Cell<u32>,
451
452 automatic_retransmission: Cell<bool>,
454 automatic_wake_up: Cell<bool>,
455 operating_mode: OptionalCell<can::OperationMode>,
456 bit_timing: OptionalCell<can::BitTiming>,
457
458 controller_client: OptionalCell<&'static dyn can::ControllerClient>,
460 receive_client:
461 OptionalCell<&'static dyn can::ReceiveClient<{ can::STANDARD_CAN_PACKET_SIZE }>>,
462 transmit_client:
463 OptionalCell<&'static dyn can::TransmitClient<{ can::STANDARD_CAN_PACKET_SIZE }>>,
464
465 rx_buffer: TakeCell<'static, [u8; can::STANDARD_CAN_PACKET_SIZE]>,
467 tx_buffer: TakeCell<'static, [u8; can::STANDARD_CAN_PACKET_SIZE]>,
468
469 deferred_call: DeferredCall,
470 deferred_action: OptionalCell<AsyncAction>,
472}
473
474impl<'a> Can<'a> {
475 pub fn new(clocks: &'a dyn Stm32f4Clocks, registers: StaticRef<Registers>) -> Can<'a> {
476 Can {
477 registers,
478 clock: CanClock(phclk::PeripheralClock::new(
479 phclk::PeripheralClockType::APB1(phclk::PCLK1::CAN1),
480 clocks,
481 )),
482 can_state: Cell::new(CanState::Sleep),
483 error_interrupt_counter: Cell::new(0),
484 fifo0_interrupt_counter: Cell::new(0),
485 fifo1_interrupt_counter: Cell::new(0),
486 failed_messages: Cell::new(0),
487 automatic_retransmission: Cell::new(false),
488 automatic_wake_up: Cell::new(false),
489 operating_mode: OptionalCell::empty(),
490 bit_timing: OptionalCell::empty(),
491 controller_client: OptionalCell::empty(),
492 receive_client: OptionalCell::empty(),
493 transmit_client: OptionalCell::empty(),
494 rx_buffer: TakeCell::empty(),
495 tx_buffer: TakeCell::empty(),
496 deferred_call: DeferredCall::new(),
497 deferred_action: OptionalCell::empty(),
498 }
499 }
500
501 fn wait_for(times: usize, f: impl Fn() -> bool) -> bool {
509 for _ in 0..times {
510 if f() {
511 return true;
512 }
513 }
514
515 false
516 }
517
518 pub fn enable(&self) -> Result<(), kernel::ErrorCode> {
521 self.registers.can_mcr.modify(CAN_MCR::SLEEP::CLEAR);
523
524 self.registers.can_mcr.modify(CAN_MCR::INRQ::SET);
526
527 if !Can::wait_for(20000, || self.registers.can_msr.is_set(CAN_MSR::INAK)) {
532 return Err(kernel::ErrorCode::FAIL);
533 }
534
535 self.can_state.set(CanState::Initialization);
536
537 if !Can::wait_for(20000, || !self.registers.can_msr.is_set(CAN_MSR::SLAK)) {
542 return Err(kernel::ErrorCode::FAIL);
543 }
544
545 self.registers.can_mcr.modify(CAN_MCR::TTCM::CLEAR);
547 self.registers.can_mcr.modify(CAN_MCR::ABOM::CLEAR);
548 self.registers.can_mcr.modify(CAN_MCR::RFLM::CLEAR);
549 self.registers.can_mcr.modify(CAN_MCR::TXFP::CLEAR);
550
551 match self.automatic_retransmission.get() {
552 true => self.registers.can_mcr.modify(CAN_MCR::AWUM::SET),
553 false => self.registers.can_mcr.modify(CAN_MCR::AWUM::CLEAR),
554 }
555
556 match self.automatic_wake_up.get() {
557 true => self.registers.can_mcr.modify(CAN_MCR::NART::CLEAR),
558 false => self.registers.can_mcr.modify(CAN_MCR::NART::SET),
559 }
560
561 if let Some(operating_mode_settings) = self.operating_mode.get() {
562 match operating_mode_settings {
563 can::OperationMode::Loopback => self.registers.can_btr.modify(CAN_BTR::LBKM::SET),
564 can::OperationMode::Monitoring => self.registers.can_btr.modify(CAN_BTR::SILM::SET),
565 can::OperationMode::Freeze => return Err(kernel::ErrorCode::INVAL),
566 _ => {}
567 }
568 }
569
570 if let Some(bit_timing_settings) = self.bit_timing.get() {
572 self.registers
573 .can_btr
574 .modify(CAN_BTR::TS1.val(bit_timing_settings.segment1 as u32));
575 self.registers
576 .can_btr
577 .modify(CAN_BTR::TS2.val(bit_timing_settings.segment2 as u32));
578 self.registers
579 .can_btr
580 .modify(CAN_BTR::SJW.val(bit_timing_settings.sync_jump_width));
581 self.registers
582 .can_btr
583 .modify(CAN_BTR::BRP.val(bit_timing_settings.baud_rate_prescaler));
584 } else {
585 self.enter_sleep_mode();
586 return Err(kernel::ErrorCode::INVAL);
587 }
588
589 Ok(())
590 }
591
592 pub fn config_filter(&self, filter_info: can::FilterParameters, enable: bool) {
594 let filter_number = 1 << filter_info.number;
596
597 self.registers.can_fmr.modify(CAN_FMR::FINIT::SET);
599
600 self.registers.can_fa1r.modify(
602 CAN_FA1R::FACT.val(self.registers.can_fa1r.read(CAN_FA1R::FACT) & !filter_number),
603 );
604
605 match filter_info.scale_bits {
607 can::ScaleBits::Bits16 => {
608 self.registers.can_fs1r.modify(
609 CAN_FS1R::FSC.val(self.registers.can_fs1r.read(CAN_FS1R::FSC) | filter_number),
610 );
611 }
612 can::ScaleBits::Bits32 => {
613 self.registers.can_fs1r.modify(
614 CAN_FS1R::FSC.val(self.registers.can_fs1r.read(CAN_FS1R::FSC) & !filter_number),
615 );
616 }
617 }
618
619 self.registers.can_firx[(filter_info.number as usize) * 2].modify(CAN_FiRx::FB.val(0));
620 self.registers.can_firx[(filter_info.number as usize) * 2 + 1].modify(CAN_FiRx::FB.val(0));
621
622 match filter_info.identifier_mode {
624 can::IdentifierMode::List => {
625 self.registers.can_fm1r.modify(
626 CAN_FM1R::FBM.val(self.registers.can_fm1r.read(CAN_FM1R::FBM) | filter_number),
627 );
628 }
629 can::IdentifierMode::Mask => {
630 self.registers.can_fm1r.modify(
631 CAN_FM1R::FBM.val(self.registers.can_fm1r.read(CAN_FM1R::FBM) & !filter_number),
632 );
633 }
634 }
635
636 if filter_info.fifo_number == 0 {
638 self.registers.can_ffa1r.modify(
639 CAN_FFA1R::FFA.val(self.registers.can_ffa1r.read(CAN_FFA1R::FFA) & !filter_number),
640 );
641 } else {
642 self.registers.can_ffa1r.modify(
643 CAN_FFA1R::FFA.val(self.registers.can_ffa1r.read(CAN_FFA1R::FFA) | filter_number),
644 );
645 }
646
647 if enable {
648 self.registers.can_fa1r.modify(
649 CAN_FA1R::FACT.val(self.registers.can_fa1r.read(CAN_FA1R::FACT) | filter_number),
650 );
651 } else {
652 self.registers.can_fa1r.modify(
653 CAN_FA1R::FACT.val(self.registers.can_fa1r.read(CAN_FA1R::FACT) & !filter_number),
654 );
655 }
656 }
657
658 pub fn enable_filter_config(&self) {
659 self.registers.can_fmr.modify(CAN_FMR::FINIT::CLEAR);
661 }
662
663 pub fn enter_normal_mode(&self) -> Result<(), kernel::ErrorCode> {
664 self.registers.can_mcr.modify(CAN_MCR::INRQ::CLEAR);
666
667 if !Can::wait_for(20000, || !self.registers.can_msr.is_set(CAN_MSR::INAK)) {
672 return Err(kernel::ErrorCode::FAIL);
673 }
674
675 self.can_state.set(CanState::Normal);
676 Ok(())
677 }
678
679 pub fn enter_sleep_mode(&self) {
680 self.disable_irqs();
682 self.registers.can_mcr.modify(CAN_MCR::SLEEP::SET);
683 self.can_state.set(CanState::Sleep);
684 }
685
686 pub fn send_8byte_message(
688 &self,
689 id: can::Id,
690 dlc: usize,
691 rtr: u8,
692 ) -> Result<(), kernel::ErrorCode> {
693 self.enable_irq(CanInterruptMode::ErrorAndStatusChangeInterrupt);
694 if self.can_state.get() == CanState::Normal {
695 if let Some(tx_mailbox) = self.find_empty_mailbox() {
696 match id {
698 can::Id::Standard(id) => {
699 self.registers.can_tx_mailbox[tx_mailbox]
700 .can_tir
701 .modify(CAN_TIxR::IDE::CLEAR);
702 self.registers.can_tx_mailbox[tx_mailbox]
703 .can_tir
704 .modify(CAN_TIxR::STID.val(id as u32 & 0xeff));
705 self.registers.can_tx_mailbox[tx_mailbox]
706 .can_tir
707 .modify(CAN_TIxR::EXID.val(0));
708 }
709 can::Id::Extended(id) => {
710 self.registers.can_tx_mailbox[tx_mailbox]
711 .can_tir
712 .modify(CAN_TIxR::IDE::SET);
713 self.registers.can_tx_mailbox[tx_mailbox]
714 .can_tir
715 .modify(CAN_TIxR::STID.val((id & 0xffc0000) >> 18));
716 self.registers.can_tx_mailbox[tx_mailbox]
717 .can_tir
718 .modify(CAN_TIxR::EXID.val(id & 0x003fffff));
719 }
720 }
721 self.registers.can_tx_mailbox[tx_mailbox]
723 .can_tir
724 .modify(CAN_TIxR::RTR.val(rtr.into()));
725 self.registers.can_tx_mailbox[tx_mailbox]
727 .can_tdtr
728 .modify(CAN_TDTxR::DLC.val(dlc as u32));
729 match self.tx_buffer.map(|tx| {
731 self.registers.can_tx_mailbox[tx_mailbox]
732 .can_tdlr
733 .modify(CAN_TDLxR::DATA0.val(tx[0].into()));
734 self.registers.can_tx_mailbox[tx_mailbox]
735 .can_tdlr
736 .modify(CAN_TDLxR::DATA1.val(tx[1].into()));
737 self.registers.can_tx_mailbox[tx_mailbox]
738 .can_tdlr
739 .modify(CAN_TDLxR::DATA2.val(tx[2].into()));
740 self.registers.can_tx_mailbox[tx_mailbox]
741 .can_tdlr
742 .modify(CAN_TDLxR::DATA3.val(tx[3].into()));
743 self.registers.can_tx_mailbox[tx_mailbox]
745 .can_tdhr
746 .modify(CAN_TDHxR::DATA4.val(tx[4].into()));
747 self.registers.can_tx_mailbox[tx_mailbox]
748 .can_tdhr
749 .modify(CAN_TDHxR::DATA5.val(tx[5].into()));
750 self.registers.can_tx_mailbox[tx_mailbox]
751 .can_tdhr
752 .modify(CAN_TDHxR::DATA6.val(tx[6].into()));
753 self.registers.can_tx_mailbox[tx_mailbox]
754 .can_tdhr
755 .modify(CAN_TDHxR::DATA7.val(tx[7].into()));
756
757 self.registers.can_tx_mailbox[tx_mailbox]
758 .can_tir
759 .modify(CAN_TIxR::TXRQ::SET);
760 }) {
761 Some(()) => Ok(()),
762 None => Err(kernel::ErrorCode::FAIL),
763 }
764 } else {
765 self.failed_messages.replace(self.failed_messages.get() + 1);
767 Err(kernel::ErrorCode::BUSY)
768 }
769 } else {
770 Err(kernel::ErrorCode::OFF)
771 }
772 }
773
774 pub fn find_empty_mailbox(&self) -> Option<usize> {
775 if self.registers.can_tsr.read(CAN_TSR::TME0) == 1 {
776 Some(0)
777 } else if self.registers.can_tsr.read(CAN_TSR::TME1) == 1 {
778 Some(1)
779 } else if self.registers.can_tsr.read(CAN_TSR::TME2) == 1 {
780 Some(2)
781 } else {
782 None
783 }
784 }
785
786 pub fn is_enabled_clock(&self) -> bool {
787 self.clock.is_enabled()
788 }
789
790 pub fn enable_clock(&self) {
791 self.clock.enable();
792 }
793
794 pub fn disable_clock(&self) {
795 self.clock.disable();
796 }
797
798 pub fn handle_transmit_interrupt(&self) {
801 let mut state = Ok(());
802 if self.registers.can_esr.read(CAN_ESR::BOFF) == 1 {
803 state = Err(can::Error::BusOff)
804 } else {
805 if self.registers.can_tsr.read(CAN_TSR::RQCP0) == 1 {
806 state = if self.registers.can_tsr.read(CAN_TSR::TXOK0) == 1 {
808 Ok(())
809 } else if self.registers.can_tsr.read(CAN_TSR::TERR0) == 1 {
810 Err(can::Error::Transmission)
811 } else if self.registers.can_tsr.read(CAN_TSR::ALST0) == 1 {
812 Err(can::Error::ArbitrationLost)
813 } else {
814 Ok(())
815 };
816 self.registers.can_tsr.modify(CAN_TSR::RQCP0::SET);
818 }
819 if self.registers.can_tsr.read(CAN_TSR::RQCP1) == 1 {
820 state = if self.registers.can_tsr.read(CAN_TSR::TXOK1) == 1 {
821 Ok(())
822 } else if self.registers.can_tsr.read(CAN_TSR::TERR1) == 1 {
823 Err(can::Error::Transmission)
824 } else if self.registers.can_tsr.read(CAN_TSR::ALST1) == 1 {
825 Err(can::Error::ArbitrationLost)
826 } else {
827 Ok(())
828 };
829 self.registers.can_tsr.modify(CAN_TSR::RQCP1::SET);
831 }
832 if self.registers.can_tsr.read(CAN_TSR::RQCP2) == 1 {
833 state = if self.registers.can_tsr.read(CAN_TSR::TXOK2) == 1 {
834 Ok(())
835 } else if self.registers.can_tsr.read(CAN_TSR::TERR2) == 1 {
836 Err(can::Error::Transmission)
837 } else if self.registers.can_tsr.read(CAN_TSR::ALST2) == 1 {
838 Err(can::Error::ArbitrationLost)
839 } else {
840 Ok(())
841 };
842 self.registers.can_tsr.modify(CAN_TSR::RQCP2::SET);
844 }
845 }
846
847 if let Err(err) = state {
848 self.can_state.set(CanState::RunningError(err))
849 }
850
851 self.transmit_client.map(|transmit_client| {
852 if let Some(buf) = self.tx_buffer.take() {
853 transmit_client.transmit_complete(state, buf)
854 }
855 });
856 }
857
858 pub fn process_received_message(
859 &self,
860 rx_mailbox: usize,
861 ) -> (can::Id, usize, [u8; can::STANDARD_CAN_PACKET_SIZE]) {
862 let message_id = if self.registers.can_rx_mailbox[rx_mailbox]
863 .can_rir
864 .read(CAN_RIxR::IDE)
865 == 0
866 {
867 can::Id::Standard(
868 self.registers.can_rx_mailbox[rx_mailbox]
869 .can_rir
870 .read(CAN_RIxR::STID) as u16,
871 )
872 } else {
873 can::Id::Extended(
874 (self.registers.can_rx_mailbox[rx_mailbox]
875 .can_rir
876 .read(CAN_RIxR::STID)
877 << 18)
878 | (self.registers.can_rx_mailbox[rx_mailbox]
879 .can_rir
880 .read(CAN_RIxR::EXID)),
881 )
882 };
883 let message_length = self.registers.can_rx_mailbox[rx_mailbox]
884 .can_rdtr
885 .read(CAN_RDTxR::DLC) as usize;
886 let recv: u64 = ((self.registers.can_rx_mailbox[0].can_rdhr.get() as u64) << 32)
887 | (self.registers.can_rx_mailbox[0].can_rdlr.get() as u64);
888 let rx_buf = recv.to_le_bytes();
889 self.rx_buffer.map(|rx| {
890 rx[..8].copy_from_slice(&rx_buf[..8]);
891 });
892
893 (message_id, message_length, rx_buf)
894 }
895
896 pub fn handle_fifo0_interrupt(&self) {
897 if self.registers.can_rf0r.read(CAN_RF0R::FULL0) == 1 {
898 self.registers.can_rf0r.modify(CAN_RF0R::FULL0::SET);
899 }
900
901 if self.registers.can_rf0r.read(CAN_RF0R::FOVR0) == 1 {
902 self.registers.can_rf0r.modify(CAN_RF0R::FOVR0::SET);
903 }
904
905 if self.registers.can_rf0r.read(CAN_RF0R::FMP0) != 0 {
906 let (message_id, message_length, mut rx_buf) = self.process_received_message(0);
907
908 self.receive_client.map(|receive_client| {
909 receive_client.message_received(message_id, &mut rx_buf, message_length, Ok(()))
910 });
911 self.fifo0_interrupt_counter
912 .replace(self.fifo0_interrupt_counter.get() + 1);
913
914 self.registers.can_rf0r.modify(CAN_RF0R::RFOM0::SET);
916 }
917 }
918
919 pub fn handle_fifo1_interrupt(&self) {
920 if self.registers.can_rf1r.read(CAN_RF1R::FULL1) == 1 {
921 self.registers.can_rf1r.modify(CAN_RF1R::FULL1::SET);
922 }
923
924 if self.registers.can_rf1r.read(CAN_RF1R::FOVR1) == 1 {
925 self.registers.can_rf1r.modify(CAN_RF1R::FOVR1::SET);
926 }
927
928 if self.registers.can_rf1r.read(CAN_RF1R::FMP1) != 0 {
929 self.fifo1_interrupt_counter
930 .replace(self.fifo1_interrupt_counter.get() + 1);
931 let (message_id, message_length, mut rx_buf) = self.process_received_message(1);
932 self.receive_client.map(|receive_client| {
933 receive_client.message_received(message_id, &mut rx_buf, message_length, Ok(()))
934 });
935
936 self.registers.can_rf1r.modify(CAN_RF1R::RFOM1::SET);
938 }
939 }
940
941 pub fn handle_error_status_interrupt(&self) {
942 if self.registers.can_msr.read(CAN_MSR::WKUI) == 1 {
944 self.registers.can_msr.modify(CAN_MSR::WKUI::SET);
946 }
947 if self.registers.can_msr.read(CAN_MSR::SLAKI) == 1 {
948 self.registers.can_msr.modify(CAN_MSR::SLAKI::SET);
950 }
951
952 if self.registers.can_esr.read(CAN_ESR::EWGF) == 1 {
955 self.can_state
956 .set(CanState::RunningError(can::Error::Warning));
957 }
958 if self.registers.can_esr.read(CAN_ESR::EPVF) == 1 {
960 self.can_state
961 .set(CanState::RunningError(can::Error::Passive));
962 }
963 if self.registers.can_esr.read(CAN_ESR::BOFF) == 1 {
965 self.can_state
966 .set(CanState::RunningError(can::Error::BusOff));
967 }
968 match self.registers.can_esr.read(CAN_ESR::LEC) {
970 0x001 => self
971 .can_state
972 .set(CanState::RunningError(can::Error::Stuff)),
973 0x010 => self.can_state.set(CanState::RunningError(can::Error::Form)),
974 0x011 => self.can_state.set(CanState::RunningError(can::Error::Ack)),
975 0x100 => self
976 .can_state
977 .set(CanState::RunningError(can::Error::BitRecessive)),
978 0x101 => self
979 .can_state
980 .set(CanState::RunningError(can::Error::BitDominant)),
981 0x110 => self.can_state.set(CanState::RunningError(can::Error::Crc)),
982 0x111 => self
983 .can_state
984 .set(CanState::RunningError(can::Error::SetBySoftware)),
985 _ => {}
986 }
987
988 self.error_interrupt_counter
989 .replace(self.error_interrupt_counter.get() + 1);
990
991 if let CanState::RunningError(err) = self.can_state.get() {
992 self.controller_client.map(|controller_client| {
993 controller_client.state_changed(kernel::hil::can::State::Error(err));
994 });
995 }
996 }
997
998 pub fn enable_irq(&self, interrupt: CanInterruptMode) {
999 match interrupt {
1000 CanInterruptMode::TransmitInterrupt => {
1001 self.registers.can_ier.modify(CAN_IER::TMEIE::SET);
1002 }
1003 CanInterruptMode::Fifo0Interrupt => {
1004 self.registers.can_ier.modify(CAN_IER::FMPIE0::SET);
1005 self.registers.can_ier.modify(CAN_IER::FFIE0::SET);
1006 self.registers.can_ier.modify(CAN_IER::FOVIE0::SET);
1007 }
1008 CanInterruptMode::Fifo1Interrupt => {
1009 self.registers.can_ier.modify(CAN_IER::FMPIE1::SET);
1010 self.registers.can_ier.modify(CAN_IER::FFIE1::SET);
1011 self.registers.can_ier.modify(CAN_IER::FOVIE1::SET);
1012 }
1013 CanInterruptMode::ErrorAndStatusChangeInterrupt => {
1014 self.registers.can_ier.modify(CAN_IER::ERRIE::SET);
1015 self.registers.can_ier.modify(CAN_IER::EWGIE::SET);
1016 self.registers.can_ier.modify(CAN_IER::EPVIE::SET);
1017 self.registers.can_ier.modify(CAN_IER::BOFIE::SET);
1018 self.registers.can_ier.modify(CAN_IER::LECIE::SET);
1019 self.registers.can_ier.modify(CAN_IER::WKUIE::SET);
1020 self.registers.can_ier.modify(CAN_IER::SLKIE::SET);
1021 }
1022 }
1023 }
1024
1025 pub fn disable_irq(&self, interrupt: CanInterruptMode) {
1026 match interrupt {
1027 CanInterruptMode::TransmitInterrupt => {
1028 self.registers.can_ier.modify(CAN_IER::TMEIE::CLEAR);
1029 }
1030 CanInterruptMode::Fifo0Interrupt => {
1031 self.registers.can_ier.modify(CAN_IER::FMPIE0::CLEAR);
1032 self.registers.can_ier.modify(CAN_IER::FFIE0::CLEAR);
1033 self.registers.can_ier.modify(CAN_IER::FOVIE0::CLEAR);
1034 }
1035 CanInterruptMode::Fifo1Interrupt => {
1036 self.registers.can_ier.modify(CAN_IER::FMPIE1::CLEAR);
1037 self.registers.can_ier.modify(CAN_IER::FFIE1::CLEAR);
1038 self.registers.can_ier.modify(CAN_IER::FOVIE1::CLEAR);
1039 }
1040 CanInterruptMode::ErrorAndStatusChangeInterrupt => {
1041 self.registers.can_ier.modify(CAN_IER::ERRIE::CLEAR);
1042 self.registers.can_ier.modify(CAN_IER::EWGIE::CLEAR);
1043 self.registers.can_ier.modify(CAN_IER::EPVIE::CLEAR);
1044 self.registers.can_ier.modify(CAN_IER::BOFIE::CLEAR);
1045 self.registers.can_ier.modify(CAN_IER::LECIE::CLEAR);
1046 self.registers.can_ier.modify(CAN_IER::WKUIE::CLEAR);
1047 self.registers.can_ier.modify(CAN_IER::SLKIE::CLEAR);
1048 }
1049 }
1050 }
1051
1052 pub fn enable_irqs(&self) {
1053 self.enable_irq(CanInterruptMode::TransmitInterrupt);
1054 self.enable_irq(CanInterruptMode::Fifo0Interrupt);
1055 self.enable_irq(CanInterruptMode::Fifo1Interrupt);
1056 self.enable_irq(CanInterruptMode::ErrorAndStatusChangeInterrupt);
1057 }
1058
1059 pub fn disable_irqs(&self) {
1060 self.disable_irq(CanInterruptMode::TransmitInterrupt);
1061 self.disable_irq(CanInterruptMode::Fifo0Interrupt);
1062 self.disable_irq(CanInterruptMode::Fifo1Interrupt);
1063 self.disable_irq(CanInterruptMode::ErrorAndStatusChangeInterrupt);
1064 }
1065}
1066
1067impl DeferredCallClient for Can<'_> {
1068 fn register(&'static self) {
1069 self.deferred_call.register(self)
1070 }
1071
1072 fn handle_deferred_call(&self) {
1073 match self.deferred_action.take() {
1074 Some(action) => match action {
1075 AsyncAction::Enable => {
1076 if let Err(enable_err) = self.enter_normal_mode() {
1077 self.controller_client.map(|controller_client| {
1078 controller_client.state_changed(self.can_state.get().into());
1079 controller_client.enabled(Err(enable_err));
1080 });
1081 }
1082 self.controller_client.map(|controller_client| {
1083 controller_client.state_changed(can::State::Running);
1084 controller_client.enabled(Ok(()));
1085 });
1086 }
1087 AsyncAction::AbortReceive => {
1088 if let Some(rx) = self.rx_buffer.take() {
1089 self.receive_client
1090 .map(|receive_client| receive_client.stopped(rx));
1091 }
1092 }
1093 AsyncAction::Disabled => {
1094 self.controller_client.map(|controller_client| {
1095 controller_client.state_changed(self.can_state.get().into());
1096 controller_client.disabled(Ok(()));
1097 });
1098 }
1099 AsyncAction::EnableError(err) => {
1100 self.controller_client.map(|controller_client| {
1101 controller_client.state_changed(self.can_state.get().into());
1102 controller_client.enabled(Err(err));
1103 });
1104 }
1105 },
1106 None => todo!(),
1108 }
1109 }
1110}
1111
1112struct CanClock<'a>(phclk::PeripheralClock<'a>);
1113
1114impl ClockInterface for CanClock<'_> {
1115 fn is_enabled(&self) -> bool {
1116 self.0.is_enabled()
1117 }
1118
1119 fn enable(&self) {
1120 self.0.enable();
1121 }
1122
1123 fn disable(&self) {
1124 self.0.disable();
1125 }
1126}
1127
1128impl can::Configure for Can<'_> {
1129 const MIN_BIT_TIMINGS: can::BitTiming = can::BitTiming {
1130 segment1: BitSegment1::CanBtrTs1Min as u8,
1131 segment2: BitSegment2::CanBtrTs2Min as u8,
1132 propagation: 0,
1133 sync_jump_width: SynchronizationJumpWidth::CanBtrSjwMin as u32,
1134 baud_rate_prescaler: BRP_MIN_STM32,
1135 };
1136
1137 const MAX_BIT_TIMINGS: can::BitTiming = can::BitTiming {
1138 segment1: BitSegment1::CanBtrTs1Max as u8,
1139 segment2: BitSegment2::CanBtrTs2Max as u8,
1140 propagation: 0,
1141 sync_jump_width: SynchronizationJumpWidth::CanBtrSjwMax as u32,
1142 baud_rate_prescaler: BRP_MAX_STM32,
1143 };
1144
1145 const SYNC_SEG: u8 = 1;
1146
1147 fn set_bitrate(&self, bitrate: u32) -> Result<(), kernel::ErrorCode> {
1148 let bit_timing = Self::bit_timing_for_bitrate(16_000_000, bitrate)?;
1149 self.set_bit_timing(bit_timing)
1150 }
1151
1152 fn set_bit_timing(&self, bit_timing: can::BitTiming) -> Result<(), kernel::ErrorCode> {
1153 match self.can_state.get() {
1154 CanState::Sleep => {
1155 self.bit_timing.set(bit_timing);
1156 Ok(())
1157 }
1158 CanState::Normal | CanState::Initialization | CanState::RunningError(_) => {
1159 Err(kernel::ErrorCode::BUSY)
1160 }
1161 }
1162 }
1163
1164 fn set_operation_mode(&self, mode: can::OperationMode) -> Result<(), kernel::ErrorCode> {
1165 match self.can_state.get() {
1166 CanState::Sleep => {
1167 self.operating_mode.set(mode);
1168 Ok(())
1169 }
1170 CanState::Normal | CanState::Initialization | CanState::RunningError(_) => {
1171 Err(kernel::ErrorCode::BUSY)
1172 }
1173 }
1174 }
1175
1176 fn get_bit_timing(&self) -> Result<can::BitTiming, kernel::ErrorCode> {
1177 if let Some(bit_timing) = self.bit_timing.get() {
1178 Ok(bit_timing)
1179 } else {
1180 Err(kernel::ErrorCode::INVAL)
1181 }
1182 }
1183
1184 fn get_operation_mode(&self) -> Result<can::OperationMode, kernel::ErrorCode> {
1185 if let Some(operation_mode) = self.operating_mode.get() {
1186 Ok(operation_mode)
1187 } else {
1188 Err(kernel::ErrorCode::INVAL)
1189 }
1190 }
1191
1192 fn set_automatic_retransmission(&self, automatic: bool) -> Result<(), kernel::ErrorCode> {
1193 match self.can_state.get() {
1194 CanState::Sleep => {
1195 self.automatic_retransmission.replace(automatic);
1196 Ok(())
1197 }
1198 CanState::Normal | CanState::Initialization | CanState::RunningError(_) => {
1199 Err(kernel::ErrorCode::BUSY)
1200 }
1201 }
1202 }
1203
1204 fn set_wake_up(&self, wake_up: bool) -> Result<(), kernel::ErrorCode> {
1205 match self.can_state.get() {
1206 CanState::Sleep => {
1207 self.automatic_wake_up.replace(wake_up);
1208 Ok(())
1209 }
1210 CanState::Normal | CanState::Initialization | CanState::RunningError(_) => {
1211 Err(kernel::ErrorCode::BUSY)
1212 }
1213 }
1214 }
1215
1216 fn get_automatic_retransmission(&self) -> Result<bool, kernel::ErrorCode> {
1217 Ok(self.automatic_retransmission.get())
1218 }
1219
1220 fn get_wake_up(&self) -> Result<bool, kernel::ErrorCode> {
1221 Ok(self.automatic_wake_up.get())
1222 }
1223
1224 fn receive_fifo_count(&self) -> usize {
1225 2
1226 }
1227}
1228
1229impl can::Controller for Can<'_> {
1230 fn set_client(&self, client: Option<&'static dyn can::ControllerClient>) {
1231 if let Some(client) = client {
1232 self.controller_client.replace(client);
1233 } else {
1234 self.controller_client.clear();
1235 }
1236 }
1237
1238 fn enable(&self) -> Result<(), kernel::ErrorCode> {
1239 match self.can_state.get() {
1240 CanState::Sleep => {
1241 if self.bit_timing.is_none() || self.operating_mode.is_none() {
1242 Err(kernel::ErrorCode::INVAL)
1243 } else {
1244 let r = self.enable();
1245 if self.deferred_action.is_some() {
1247 Err(kernel::ErrorCode::BUSY)
1248 } else {
1249 match r {
1251 Ok(()) => {
1252 self.deferred_action.set(AsyncAction::Enable);
1253 }
1254 Err(err) => {
1255 self.deferred_action.set(AsyncAction::EnableError(err));
1256 }
1257 }
1258 self.deferred_call.set();
1259 r
1260 }
1261 }
1262 }
1263 CanState::Normal | CanState::Initialization => Err(kernel::ErrorCode::ALREADY),
1264 CanState::RunningError(_) => Err(kernel::ErrorCode::FAIL),
1265 }
1266 }
1267
1268 fn disable(&self) -> Result<(), kernel::ErrorCode> {
1269 match self.can_state.get() {
1270 CanState::Normal | CanState::RunningError(_) => {
1271 self.enter_sleep_mode();
1272 if self.deferred_action.is_some() {
1273 return Err(kernel::ErrorCode::BUSY);
1275 } else {
1276 self.deferred_action.set(AsyncAction::Disabled);
1278 self.deferred_call.set();
1279 }
1280 Ok(())
1281 }
1282 CanState::Sleep | CanState::Initialization => Err(kernel::ErrorCode::OFF),
1283 }
1284 }
1285
1286 fn get_state(&self) -> Result<can::State, kernel::ErrorCode> {
1287 Ok(self.can_state.get().into())
1288 }
1289}
1290
1291impl can::Transmit<{ can::STANDARD_CAN_PACKET_SIZE }> for Can<'_> {
1292 fn set_client(
1293 &self,
1294 client: Option<&'static dyn can::TransmitClient<{ can::STANDARD_CAN_PACKET_SIZE }>>,
1295 ) {
1296 if let Some(client) = client {
1297 self.transmit_client.set(client);
1298 } else {
1299 self.transmit_client.clear();
1300 }
1301 }
1302
1303 fn send(
1304 &self,
1305 id: can::Id,
1306 buffer: &'static mut [u8; can::STANDARD_CAN_PACKET_SIZE],
1307 len: usize,
1308 ) -> Result<
1309 (),
1310 (
1311 kernel::ErrorCode,
1312 &'static mut [u8; can::STANDARD_CAN_PACKET_SIZE],
1313 ),
1314 > {
1315 match self.can_state.get() {
1316 CanState::Normal | CanState::RunningError(_) => {
1317 self.tx_buffer.replace(buffer);
1318 self.enable_irq(CanInterruptMode::TransmitInterrupt);
1319 self.can_state.set(CanState::Normal);
1320 match self.send_8byte_message(id, len, 0) {
1321 Ok(()) => Ok(()),
1322 Err(err) => Err((err, self.tx_buffer.take().unwrap())),
1323 }
1324 }
1325 CanState::Sleep | CanState::Initialization => Err((kernel::ErrorCode::OFF, buffer)),
1326 }
1327 }
1328}
1329
1330impl can::Receive<{ can::STANDARD_CAN_PACKET_SIZE }> for Can<'_> {
1331 fn set_client(
1332 &self,
1333 client: Option<&'static dyn can::ReceiveClient<{ can::STANDARD_CAN_PACKET_SIZE }>>,
1334 ) {
1335 if let Some(client) = client {
1336 self.receive_client.set(client);
1337 } else {
1338 self.receive_client.clear();
1339 }
1340 }
1341
1342 fn start_receive_process(
1343 &self,
1344 buffer: &'static mut [u8; can::STANDARD_CAN_PACKET_SIZE],
1345 ) -> Result<
1346 (),
1347 (
1348 kernel::ErrorCode,
1349 &'static mut [u8; can::STANDARD_CAN_PACKET_SIZE],
1350 ),
1351 > {
1352 match self.can_state.get() {
1353 CanState::Normal | CanState::RunningError(_) => {
1354 self.can_state.set(CanState::Normal);
1355 self.config_filter(
1356 can::FilterParameters {
1357 number: 0,
1358 scale_bits: can::ScaleBits::Bits32,
1359 identifier_mode: can::IdentifierMode::Mask,
1360 fifo_number: 0,
1361 },
1362 true,
1363 );
1364 self.config_filter(
1365 can::FilterParameters {
1366 number: 1,
1367 scale_bits: can::ScaleBits::Bits32,
1368 identifier_mode: can::IdentifierMode::Mask,
1369 fifo_number: 1,
1370 },
1371 true,
1372 );
1373 self.enable_filter_config();
1374 self.enable_irq(CanInterruptMode::Fifo0Interrupt);
1375 self.enable_irq(CanInterruptMode::Fifo1Interrupt);
1376 self.rx_buffer.put(Some(buffer));
1377 Ok(())
1378 }
1379 CanState::Sleep | CanState::Initialization => Err((kernel::ErrorCode::OFF, buffer)),
1380 }
1381 }
1382
1383 fn stop_receive(&self) -> Result<(), kernel::ErrorCode> {
1384 match self.can_state.get() {
1385 CanState::Normal | CanState::RunningError(_) => {
1386 self.can_state.set(CanState::Normal);
1387 self.config_filter(
1388 can::FilterParameters {
1389 number: 0,
1390 scale_bits: can::ScaleBits::Bits32,
1391 identifier_mode: can::IdentifierMode::Mask,
1392 fifo_number: 0,
1393 },
1394 false,
1395 );
1396 self.config_filter(
1397 can::FilterParameters {
1398 number: 1,
1399 scale_bits: can::ScaleBits::Bits32,
1400 identifier_mode: can::IdentifierMode::Mask,
1401 fifo_number: 1,
1402 },
1403 false,
1404 );
1405 self.enable_filter_config();
1406 self.disable_irq(CanInterruptMode::Fifo0Interrupt);
1407 self.disable_irq(CanInterruptMode::Fifo1Interrupt);
1408 if self.deferred_action.is_some() {
1410 Err(kernel::ErrorCode::BUSY)
1411 } else if self.rx_buffer.is_none() {
1413 Err(kernel::ErrorCode::SIZE)
1414 } else {
1415 self.deferred_action.set(AsyncAction::AbortReceive);
1417 self.deferred_call.set();
1418 Ok(())
1419 }
1420 }
1421 CanState::Sleep | CanState::Initialization => Err(kernel::ErrorCode::OFF),
1422 }
1423 }
1424}