msp432/
lib.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5#![crate_name = "msp432"]
6#![crate_type = "rlib"]
7#![no_std]
8
9use cortexm4::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM4, CortexMVariant};
10
11pub mod adc;
12pub mod chip;
13pub mod cs;
14pub mod dma;
15pub mod flctl;
16pub mod gpio;
17pub mod i2c;
18pub mod nvic;
19pub mod pcm;
20pub mod ref_module;
21pub mod sysctl;
22pub mod timer;
23pub mod uart;
24pub mod usci;
25pub mod wdt;
26
27extern "C" {
28    // _estack is not really a function, but it makes the types work
29    // You should never actually invoke it!!
30    fn _estack();
31}
32
33#[cfg_attr(
34    all(target_arch = "arm", target_os = "none"),
35    link_section = ".vectors"
36)]
37// used Ensures that the symbol is kept until the final binary
38#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
39pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
40    _estack,
41    initialize_ram_jump_to_main,
42    unhandled_interrupt,          // NMI
43    CortexM4::HARD_FAULT_HANDLER, // Hard Fault
44    unhandled_interrupt,          // MemManage
45    unhandled_interrupt,          // BusFault
46    unhandled_interrupt,          // UsageFault
47    unhandled_interrupt,
48    unhandled_interrupt,
49    unhandled_interrupt,
50    unhandled_interrupt,
51    CortexM4::SVC_HANDLER, // SVC
52    unhandled_interrupt,   // DebugMon
53    unhandled_interrupt,
54    unhandled_interrupt,       // PendSV
55    CortexM4::SYSTICK_HANDLER, // SysTick
56];
57
58#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
59// used Ensures that the symbol is kept until the final binary
60#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
61pub static IRQS: [unsafe extern "C" fn(); 64] = [
62    CortexM4::GENERIC_ISR, // Power Supply System (PSS) (0)
63    CortexM4::GENERIC_ISR, // Clock System (CS) (1)
64    CortexM4::GENERIC_ISR, // Power Control Manager (PCM) (2)
65    CortexM4::GENERIC_ISR, // Watchdog Timer A (WDT_A) (3)
66    CortexM4::GENERIC_ISR, // FPU_INT, Combined interrupt from flags in FPSCR (4)
67    CortexM4::GENERIC_ISR, // FLash Controller (FLCTL) (5)
68    CortexM4::GENERIC_ISR, // Comparator E0 (6)
69    CortexM4::GENERIC_ISR, // Comparator E1 (7)
70    CortexM4::GENERIC_ISR, // Timer A0 TA0CCTL0.CCIFG (8)
71    CortexM4::GENERIC_ISR, // Timer A0 TA0CCTLx.CCIFG (x = 1 to 4), TA0CTL.TAIFG (9)
72    CortexM4::GENERIC_ISR, // Timer A1 TA1CCTL0.CCIFG (10)
73    CortexM4::GENERIC_ISR, // Timer A1 TA1CCTLx.CCIFG (x = 1 to 4), TA1CTL.TAIFG (11)
74    CortexM4::GENERIC_ISR, // Timer A2 TA2CCTL0.CCIFG (12)
75    CortexM4::GENERIC_ISR, // Timer A2 TA2CCTLx.CCIFG (x = 1 to 4), TA2CTL.TAIFG (13)
76    CortexM4::GENERIC_ISR, // Timer A3 TA3CCTL0.CCIFG (13)
77    CortexM4::GENERIC_ISR, // Timer A3 TA3CCTLx.CCIFG (x = 1 to 4), TA3CTL.TAIFG (15)
78    CortexM4::GENERIC_ISR, // eUSCI A0 (16)
79    CortexM4::GENERIC_ISR, // eUSCI A1 (17)
80    CortexM4::GENERIC_ISR, // eUSCI A2 (18)
81    CortexM4::GENERIC_ISR, // eUSCI A3 (19)
82    CortexM4::GENERIC_ISR, // eUSCI B0 (20)
83    CortexM4::GENERIC_ISR, // eUSCI B1 (21)
84    CortexM4::GENERIC_ISR, // eUSCI B2 (22)
85    CortexM4::GENERIC_ISR, // eUSCI B3 (23)
86    CortexM4::GENERIC_ISR, // Precision ADC (24)
87    CortexM4::GENERIC_ISR, // Timer32 INT1 (25)
88    CortexM4::GENERIC_ISR, // Timer32 INT2 (26)
89    CortexM4::GENERIC_ISR, // Timer32 combined interrupt (27)
90    CortexM4::GENERIC_ISR, // AES256 (28)
91    CortexM4::GENERIC_ISR, // RTC_C (29)
92    CortexM4::GENERIC_ISR, // DMA error (30)
93    CortexM4::GENERIC_ISR, // DMA INT3 (31)
94    CortexM4::GENERIC_ISR, // DMA INT2 (32)
95    CortexM4::GENERIC_ISR, // DMA INT1 (33)
96    CortexM4::GENERIC_ISR, // DMA INT0 (34)
97    CortexM4::GENERIC_ISR, // IO Port 1 (35)
98    CortexM4::GENERIC_ISR, // IO Port 2 (36)
99    CortexM4::GENERIC_ISR, // IO Port 3 (37)
100    CortexM4::GENERIC_ISR, // IO Port 4 (38)
101    CortexM4::GENERIC_ISR, // IO Port 5 (39)
102    CortexM4::GENERIC_ISR, // IO Port 6 (40)
103    unhandled_interrupt,   // Reserved (41)
104    unhandled_interrupt,   // Reserved (42)
105    unhandled_interrupt,   // Reserved (43)
106    unhandled_interrupt,   // Reserved (44)
107    unhandled_interrupt,   // Reserved (45)
108    unhandled_interrupt,   // Reserved (46)
109    unhandled_interrupt,   // Reserved (47)
110    unhandled_interrupt,   // Reserved (48)
111    unhandled_interrupt,   // Reserved (49)
112    unhandled_interrupt,   // Reserved (50)
113    unhandled_interrupt,   // Reserved (51)
114    unhandled_interrupt,   // Reserved (52)
115    unhandled_interrupt,   // Reserved (53)
116    unhandled_interrupt,   // Reserved (54)
117    unhandled_interrupt,   // Reserved (55)
118    unhandled_interrupt,   // Reserved (56)
119    unhandled_interrupt,   // Reserved (57)
120    unhandled_interrupt,   // Reserved (58)
121    unhandled_interrupt,   // Reserved (59)
122    unhandled_interrupt,   // Reserved (60)
123    unhandled_interrupt,   // Reserved (61)
124    unhandled_interrupt,   // Reserved (62)
125    unhandled_interrupt,   // Reserved (63)
126];
127
128pub unsafe fn init() {
129    cortexm4::nvic::disable_all();
130    cortexm4::nvic::clear_all_pending();
131    cortexm4::nvic::enable_all();
132}
msp432/lib.rs

msp432/
lib.rs
