msp432/flctl.rs
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Flash Controller (FLCTL)
6
7use kernel::utilities::registers::interfaces::ReadWriteable;
8use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
9use kernel::utilities::StaticRef;
10
11const FLCTL_BASE: StaticRef<FlCtlRegisters> =
12 unsafe { StaticRef::new(0x4001_1000u32 as *const FlCtlRegisters) };
13
14register_structs! {
15 /// FLCTL
16 FlCtlRegisters {
17 /// Power Status Register
18 (0x000 => power_stat: ReadOnly<u32, FLCTL_POWER_STAT::Register>),
19 (0x004 => _reserved0),
20 /// Bank0 Read Control Register
21 (0x010 => bank0_rdctl: ReadWrite<u32, FLCTL_BANK0_RDCTL::Register>),
22 /// Bank1 Read Control Register
23 (0x014 => bank1_rdctl: ReadWrite<u32, FLCTL_BANK1_RDCTL::Register>),
24 (0x018 => _reserved1),
25 /// Read Burst/Compare Control and Status Register
26 (0x020 => rdbrst_ctlstat: ReadWrite<u32, FLCTL_RDBRST_CTLSTAT::Register>),
27 /// Read Burst/Compare Start Address Register
28 (0x024 => rdbrst_startaddr: ReadWrite<u32>),
29 /// Read Burst/Compare Length Register
30 (0x028 => rdbrst_len: ReadWrite<u32>),
31 (0x02C => _reserved2),
32 /// Read Burst/Compare Fail Address Register
33 (0x03C => rdbrst_failaddr: ReadWrite<u32>),
34 /// Read Burst/Compare Fail Count Register
35 (0x040 => rdbrst_failcnt: ReadWrite<u32>),
36 (0x044 => _reserved3),
37 /// Program Control and Status Register
38 (0x050 => prg_ctlstat: ReadWrite<u32, FLCTL_PRG_CTLSTAT::Register>),
39 /// Program Burst Control and Status Register
40 (0x054 => prgbrst_ctlstat: ReadWrite<u32, FLCTL_PRGBRST_CTLSTAT::Register>),
41 /// Program Burst Start Address Register
42 (0x058 => prgbrst_startaddr: ReadWrite<u32>),
43 (0x05C => _reserved4),
44 /// Program Burst Data0 Register0
45 (0x060 => prgbrst_data0_0: ReadWrite<u32>),
46 /// Program Burst Data0 Register1
47 (0x064 => prgbrst_data0_1: ReadWrite<u32>),
48 /// Program Burst Data0 Register2
49 (0x068 => prgbrst_data0_2: ReadWrite<u32>),
50 /// Program Burst Data0 Register3
51 (0x06C => prgbrst_data0_3: ReadWrite<u32>),
52 /// Program Burst Data1 Register0
53 (0x070 => prgbrst_data1_0: ReadWrite<u32>),
54 /// Program Burst Data1 Register1
55 (0x074 => prgbrst_data1_1: ReadWrite<u32>),
56 /// Program Burst Data1 Register2
57 (0x078 => prgbrst_data1_2: ReadWrite<u32>),
58 /// Program Burst Data1 Register3
59 (0x07C => prgbrst_data1_3: ReadWrite<u32>),
60 /// Program Burst Data2 Register0
61 (0x080 => prgbrst_data2_0: ReadWrite<u32>),
62 /// Program Burst Data2 Register1
63 (0x084 => prgbrst_data2_1: ReadWrite<u32>),
64 /// Program Burst Data2 Register2
65 (0x088 => prgbrst_data2_2: ReadWrite<u32>),
66 /// Program Burst Data2 Register3
67 (0x08C => prgbrst_data2_3: ReadWrite<u32>),
68 /// Program Burst Data3 Register0
69 (0x090 => prgbrst_data3_0: ReadWrite<u32>),
70 /// Program Burst Data3 Register1
71 (0x094 => prgbrst_data3_1: ReadWrite<u32>),
72 /// Program Burst Data3 Register2
73 (0x098 => prgbrst_data3_2: ReadWrite<u32>),
74 /// Program Burst Data3 Register3
75 (0x09C => prgbrst_data3_3: ReadWrite<u32>),
76 /// Erase Control and Status Register
77 (0x0A0 => erase_ctlstat: ReadWrite<u32, FLCTL_ERASE_CTLSTAT::Register>),
78 /// Erase Sector Address Register
79 (0x0A4 => erase_sectaddr: ReadWrite<u32>),
80 (0x0A8 => _reserved5),
81 /// Information Memory Bank0 Write/Erase Protection Register
82 (0x0B0 => bank0_info_weprot: ReadWrite<u32, FLCTL_BANK0_INFO_WEPROT::Register>),
83 /// Main Memory Bank0 Write/Erase Protection Register
84 (0x0B4 => bank0_main_weprot: ReadWrite<u32, FLCTL_BANK0_MAIN_WEPROT::Register>),
85 (0x0B8 => _reserved6),
86 /// Information Memory Bank1 Write/Erase Protection Register
87 (0x0C0 => bank1_info_weprot: ReadWrite<u32, FLCTL_BANK1_INFO_WEPROT::Register>),
88 /// Main Memory Bank1 Write/Erase Protection Register
89 (0x0C4 => bank1_main_weprot: ReadWrite<u32, FLCTL_BANK1_MAIN_WEPROT::Register>),
90 (0x0C8 => _reserved7),
91 /// Benchmark Control and Status Register
92 (0x0D0 => bmrk_ctlstat: ReadWrite<u32, FLCTL_BMRK_CTLSTAT::Register>),
93 /// Benchmark Instruction Fetch Count Register
94 (0x0D4 => bmrk_ifetch: ReadWrite<u32>),
95 /// Benchmark Data Read Count Register
96 (0x0D8 => bmrk_dread: ReadWrite<u32>),
97 /// Benchmark Count Compare Register
98 (0x0DC => bmrk_cmp: ReadWrite<u32>),
99 (0x0E0 => _reserved8),
100 /// Interrupt Flag Register
101 (0x0F0 => ifg: ReadWrite<u32, FLCTL_IFG::Register>),
102 /// Interrupt Enable Register
103 (0x0F4 => ie: ReadWrite<u32, FLCTL_IE::Register>),
104 /// Clear Interrupt Flag Register
105 (0x0F8 => clrifg: ReadWrite<u32, FLCTL_CLRIFG::Register>),
106 /// Set Interrupt Flag Register
107 (0x0FC => setifg: ReadWrite<u32, FLCTL_SETIFG::Register>),
108 /// Read Timing Control Register
109 (0x100 => read_timctl: ReadOnly<u32, FLCTL_READ_TIMCTL::Register>),
110 /// Read Margin Timing Control Register
111 (0x104 => readmargin_timctl: ReadOnly<u32>),
112 /// Program Verify Timing Control Register
113 (0x108 => prgver_timctl: ReadOnly<u32, FLCTL_PRGVER_TIMCTL::Register>),
114 /// Erase Verify Timing Control Register
115 (0x10C => ersver_timctl: ReadOnly<u32>),
116 /// Leakage Verify Timing Control Register
117 (0x110 => lkgver_timctl: ReadOnly<u32>),
118 /// Program Timing Control Register
119 (0x114 => program_timctl: ReadOnly<u32, FLCTL_PROGRAM_TIMCTL::Register>),
120 /// Erase Timing Control Register
121 (0x118 => erase_timctl: ReadOnly<u32, FLCTL_ERASE_TIMCTL::Register>),
122 /// Mass Erase Timing Control Register
123 (0x11C => masserase_timctl: ReadOnly<u32, FLCTL_MASSERASE_TIMCTL::Register>),
124 /// Burst Program Timing Control Register
125 (0x120 => burstprg_timctl: ReadOnly<u32>),
126 (0x124 => @END),
127 }
128}
129
130register_bitfields![u32,
131 FLCTL_POWER_STAT [
132 /// Flash power status
133 PSTAT OFFSET(0) NUMBITS(3) [
134 /// Flash IP in power-down mode
135 FlashIPInPowerDownMode = 0,
136 /// Flash IP Vdd domain power-up in progress
137 FlashIPVddDomainPowerUpInProgress = 1,
138 /// PSS LDO_GOOD, IREF_OK and VREF_OK check in progress
139 PSSLDO_GOODIREF_OKAndVREF_OKCheckInProgress = 2,
140 /// Flash IP SAFE_LV check in progress
141 FlashIPSAFE_LVCheckInProgress = 3,
142 /// Flash IP Active
143 FlashIPActive = 4,
144 /// Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes.
145 FlashIPActiveInLowFrequencyActiveAndLowFrequencyLPM0Modes = 5,
146 /// Flash IP in Standby mode
147 FlashIPInStandbyMode = 6,
148 /// Flash IP in Current mirror boost state
149 FlashIPInCurrentMirrorBoostState = 7
150 ],
151 /// PSS FLDO GOOD status
152 LDOSTAT OFFSET(3) NUMBITS(1) [
153 /// FLDO not GOOD
154 FLDONotGOOD = 0,
155 /// FLDO GOOD
156 FLDOGOOD = 1
157 ],
158 /// PSS VREF stable status
159 VREFSTAT OFFSET(4) NUMBITS(1) [
160 /// Flash LDO not stable
161 FlashLDONotStable = 0,
162 /// Flash LDO stable
163 FlashLDOStable = 1
164 ],
165 /// PSS IREF stable status
166 IREFSTAT OFFSET(5) NUMBITS(1) [
167 /// IREF not stable
168 IREFNotStable = 0,
169 /// IREF stable
170 IREFStable = 1
171 ],
172 /// PSS trim done status
173 TRIMSTAT OFFSET(6) NUMBITS(1) [
174 /// PSS trim not complete
175 PSSTrimNotComplete = 0,
176 /// PSS trim complete
177 PSSTrimComplete = 1
178 ],
179 /// Indicates if Flash is being accessed in 2T mode
180 RD_2T OFFSET(7) NUMBITS(1) [
181 /// Flash reads are in 1T mode
182 FlashReadsAreIn1TMode = 0,
183 /// Flash reads are in 2T mode
184 FlashReadsAreIn2TMode = 1
185 ]
186 ],
187 FLCTL_BANK0_RDCTL [
188 /// Flash read mode control setting for Bank 0
189 RD_MODE OFFSET(0) NUMBITS(4) [
190 /// Normal read mode
191 NormalReadMode = 0,
192 /// Read Margin 0
193 ReadMargin0 = 1,
194 /// Read Margin 1
195 ReadMargin1 = 2,
196 /// Program Verify
197 ProgramVerify = 3,
198 /// Erase Verify
199 EraseVerify = 4,
200 /// Leakage Verify
201 LeakageVerify = 5,
202 /// Read Margin 0B
203 ReadMargin0B = 9,
204 /// Read Margin 1B
205 ReadMargin1B = 10
206 ],
207 /// Enables read buffering feature for instruction fetches to this Bank
208 BUFI OFFSET(4) NUMBITS(1) [],
209 /// Enables read buffering feature for data reads to this Bank
210 BUFD OFFSET(5) NUMBITS(1) [],
211 /// Number of wait states for read
212 WAIT OFFSET(12) NUMBITS(4) [
213 /// 0 wait states
214 _0WaitStates = 0,
215 /// 1 wait states
216 _1WaitStates = 1,
217 /// 2 wait states
218 _2WaitStates = 2,
219 /// 3 wait states
220 _3WaitStates = 3,
221 /// 4 wait states
222 _4WaitStates = 4,
223 /// 5 wait states
224 _5WaitStates = 5,
225 /// 6 wait states
226 _6WaitStates = 6,
227 /// 7 wait states
228 _7WaitStates = 7,
229 /// 8 wait states
230 _8WaitStates = 8,
231 /// 9 wait states
232 _9WaitStates = 9,
233 /// 10 wait states
234 _10WaitStates = 10,
235 /// 11 wait states
236 _11WaitStates = 11,
237 /// 12 wait states
238 _12WaitStates = 12,
239 /// 13 wait states
240 _13WaitStates = 13,
241 /// 14 wait states
242 _14WaitStates = 14,
243 /// 15 wait states
244 _15WaitStates = 15
245 ],
246 /// Read mode
247 RD_MODE_STATUS OFFSET(16) NUMBITS(4) [
248 /// Normal read mode
249 NormalReadMode = 0,
250 /// Read Margin 0
251 ReadMargin0 = 1,
252 /// Read Margin 1
253 ReadMargin1 = 2,
254 /// Program Verify
255 ProgramVerify = 3,
256 /// Erase Verify
257 EraseVerify = 4,
258 /// Leakage Verify
259 LeakageVerify = 5,
260 /// Read Margin 0B
261 ReadMargin0B = 9,
262 /// Read Margin 1B
263 ReadMargin1B = 10
264 ]
265 ],
266 FLCTL_BANK1_RDCTL [
267 /// Flash read mode control setting for Bank 0
268 RD_MODE OFFSET(0) NUMBITS(4) [
269 /// Normal read mode
270 NormalReadMode = 0,
271 /// Read Margin 0
272 ReadMargin0 = 1,
273 /// Read Margin 1
274 ReadMargin1 = 2,
275 /// Program Verify
276 ProgramVerify = 3,
277 /// Erase Verify
278 EraseVerify = 4,
279 /// Leakage Verify
280 LeakageVerify = 5,
281 /// Read Margin 0B
282 ReadMargin0B = 9,
283 /// Read Margin 1B
284 ReadMargin1B = 10
285 ],
286 /// Enables read buffering feature for instruction fetches to this Bank
287 BUFI OFFSET(4) NUMBITS(1) [],
288 /// Enables read buffering feature for data reads to this Bank
289 BUFD OFFSET(5) NUMBITS(1) [],
290 /// Read mode
291 RD_MODE_STATUS OFFSET(16) NUMBITS(4) [
292 /// Normal read mode
293 NormalReadMode = 0,
294 /// Read Margin 0
295 ReadMargin0 = 1,
296 /// Read Margin 1
297 ReadMargin1 = 2,
298 /// Program Verify
299 ProgramVerify = 3,
300 /// Erase Verify
301 EraseVerify = 4,
302 /// Leakage Verify
303 LeakageVerify = 5,
304 /// Read Margin 0B
305 ReadMargin0B = 9,
306 /// Read Margin 1B
307 ReadMargin1B = 10
308 ],
309 /// Number of wait states for read
310 WAIT OFFSET(12) NUMBITS(4) [
311 /// 0 wait states
312 _0WaitStates = 0,
313 /// 1 wait states
314 _1WaitStates = 1,
315 /// 2 wait states
316 _2WaitStates = 2,
317 /// 3 wait states
318 _3WaitStates = 3,
319 /// 4 wait states
320 _4WaitStates = 4,
321 /// 5 wait states
322 _5WaitStates = 5,
323 /// 6 wait states
324 _6WaitStates = 6,
325 /// 7 wait states
326 _7WaitStates = 7,
327 /// 8 wait states
328 _8WaitStates = 8,
329 /// 9 wait states
330 _9WaitStates = 9,
331 /// 10 wait states
332 _10WaitStates = 10,
333 /// 11 wait states
334 _11WaitStates = 11,
335 /// 12 wait states
336 _12WaitStates = 12,
337 /// 13 wait states
338 _13WaitStates = 13,
339 /// 14 wait states
340 _14WaitStates = 14,
341 /// 15 wait states
342 _15WaitStates = 15
343 ]
344 ],
345 FLCTL_RDBRST_CTLSTAT [
346 /// Start of burst/compare operation
347 START OFFSET(0) NUMBITS(1) [],
348 /// Type of memory that burst is carried out on
349 MEM_TYPE OFFSET(1) NUMBITS(2) [
350 /// Main Memory
351 MainMemory = 0,
352 /// Information Memory
353 InformationMemory = 1,
354 /// Engineering Memory
355 EngineeringMemory = 3
356 ],
357 /// Terminate burst/compare operation
358 STOP_FAIL OFFSET(3) NUMBITS(1) [],
359 /// Data pattern used for comparison against memory read data
360 DATA_CMP OFFSET(4) NUMBITS(1) [
361 /// 0000_0000_0000_0000_0000_0000_0000_0000
362 _0000_0000_0000_0000_0000_0000_0000_0000 = 0,
363 /// FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
364 FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF = 1
365 ],
366 /// Enable comparison against test data compare registers
367 TEST_EN OFFSET(6) NUMBITS(1) [],
368 /// Status of Burst/Compare operation
369 BRST_STAT OFFSET(16) NUMBITS(2) [
370 /// Idle
371 Idle = 0,
372 /// Burst/Compare START bit written, but operation pending
373 BurstCompareSTARTBitWrittenButOperationPending = 1,
374 /// Burst/Compare in progress
375 BurstCompareInProgress = 2,
376 /// Burst complete (status of completed burst remains in this state unless explicitl
377 BRST_STAT_3 = 3
378 ],
379 /// Burst/Compare Operation encountered atleast one data
380 CMP_ERR OFFSET(18) NUMBITS(1) [],
381 /// Burst/Compare Operation was terminated due to access to
382 ADDR_ERR OFFSET(19) NUMBITS(1) [],
383 /// Clear status bits 19-16 of this register
384 CLR_STAT OFFSET(23) NUMBITS(1) []
385 ],
386 FLCTL_PRG_CTLSTAT [
387 /// Master control for all word program operations
388 ENABLE OFFSET(0) NUMBITS(1) [
389 /// Word program operation disabled
390 WordProgramOperationDisabled = 0,
391 /// Word program operation enabled
392 WordProgramOperationEnabled = 1
393 ],
394 /// Write mode
395 MODE OFFSET(1) NUMBITS(1) [
396 /// Write immediate mode. Starts program operation immediately on each write to the
397 WriteImmediateModeStartsProgramOperationImmediatelyOnEachWriteToTheFlash = 0,
398 /// Full word write mode. Flash controller collates data over multiple writes to com
399 MODE_1 = 1
400 ],
401 /// Controls automatic pre program verify operations
402 VER_PRE OFFSET(2) NUMBITS(1) [
403 /// No pre program verification
404 NoPreProgramVerification = 0,
405 /// Pre verify feature automatically invoked for each write operation (irrespective
406 PreVerifyFeatureAutomaticallyInvokedForEachWriteOperationIrrespectiveOfTheMode = 1
407 ],
408 /// Controls automatic post program verify operations
409 VER_PST OFFSET(3) NUMBITS(1) [
410 /// No post program verification
411 NoPostProgramVerification = 0,
412 /// Post verify feature automatically invoked for each write operation (irrespective
413 PostVerifyFeatureAutomaticallyInvokedForEachWriteOperationIrrespectiveOfTheMode = 1
414 ],
415 /// Status of program operations in the Flash memory
416 STATUS OFFSET(16) NUMBITS(2) [
417 /// Idle (no program operation currently active)
418 IdleNoProgramOperationCurrentlyActive = 0,
419 /// Single word program operation triggered, but pending
420 SingleWordProgramOperationTriggeredButPending = 1,
421 /// Single word program in progress
422 SingleWordProgramInProgress = 2
423 ],
424 /// Bank active
425 BNK_ACT OFFSET(18) NUMBITS(1) [
426 /// Word in Bank0 being programmed
427 WordInBank0BeingProgrammed = 0,
428 /// Word in Bank1 being programmed
429 WordInBank1BeingProgrammed = 1
430 ]
431 ],
432 FLCTL_PRGBRST_CTLSTAT [
433 /// Trigger start of burst program operation
434 START OFFSET(0) NUMBITS(1) [],
435 /// Type of memory that burst program is carried out on
436 TYPE OFFSET(1) NUMBITS(2) [
437 /// Main Memory
438 MainMemory = 0,
439 /// Information Memory
440 InformationMemory = 1,
441 /// Engineering Memory
442 EngineeringMemory = 3
443 ],
444 /// Length of burst
445 LEN OFFSET(3) NUMBITS(3) [
446 /// No burst operation
447 NoBurstOperation = 0,
448 /// 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR R
449 _1WordBurstOf128BitsStartingWithAddressInTheFLCTL_PRGBRST_STARTADDRRegister = 1,
450 /// 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Reg
451 _2128BitsBurstWriteStartingWithAddressInTheFLCTL_PRGBRST_STARTADDRRegister = 2,
452 /// 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Reg
453 _3128BitsBurstWriteStartingWithAddressInTheFLCTL_PRGBRST_STARTADDRRegister = 3,
454 /// 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Reg
455 _4128BitsBurstWriteStartingWithAddressInTheFLCTL_PRGBRST_STARTADDRRegister = 4
456 ],
457 /// Auto-Verify operation before the Burst Program
458 AUTO_PRE OFFSET(6) NUMBITS(1) [
459 /// No program verify operations carried out
460 NoProgramVerifyOperationsCarriedOut = 0,
461 /// Causes an automatic Burst Program Verify after the Burst Program Operation
462 CausesAnAutomaticBurstProgramVerifyAfterTheBurstProgramOperation = 1
463 ],
464 /// Auto-Verify operation after the Burst Program
465 AUTO_PST OFFSET(7) NUMBITS(1) [
466 /// No program verify operations carried out
467 NoProgramVerifyOperationsCarriedOut = 0,
468 /// Causes an automatic Burst Program Verify before the Burst Program Operation
469 CausesAnAutomaticBurstProgramVerifyBeforeTheBurstProgramOperation = 1
470 ],
471 /// Status of a Burst Operation
472 BURST_STATUS OFFSET(16) NUMBITS(3) [
473 /// Idle (Burst not active)
474 IdleBurstNotActive = 0,
475 /// Burst program started but pending
476 BurstProgramStartedButPending = 1,
477 /// Burst active, with 1st 128 bit word being written into Flash
478 BurstActiveWith1st128BitWordBeingWrittenIntoFlash = 2,
479 /// Burst active, with 2nd 128 bit word being written into Flash
480 BurstActiveWith2nd128BitWordBeingWrittenIntoFlash = 3,
481 /// Burst active, with 3rd 128 bit word being written into Flash
482 BurstActiveWith3rd128BitWordBeingWrittenIntoFlash = 4,
483 /// Burst active, with 4th 128 bit word being written into Flash
484 BurstActiveWith4th128BitWordBeingWrittenIntoFlash = 5,
485 /// Burst Complete (status of completed burst remains in this state unless explicitl
486 BURST_STATUS_7 = 7
487 ],
488 /// Burst Operation encountered preprogram auto-verify errors
489 PRE_ERR OFFSET(19) NUMBITS(1) [],
490 /// Burst Operation encountered postprogram auto-verify errors
491 PST_ERR OFFSET(20) NUMBITS(1) [],
492 /// Burst Operation was terminated due to attempted program of reserved memory
493 ADDR_ERR OFFSET(21) NUMBITS(1) [],
494 /// Clear status bits 21-16 of this register
495 CLR_STAT OFFSET(23) NUMBITS(1) []
496 ],
497 FLCTL_ERASE_CTLSTAT [
498 /// Start of Erase operation
499 START OFFSET(0) NUMBITS(1) [],
500 /// Erase mode selected by application
501 MODE OFFSET(1) NUMBITS(1) [
502 /// Sector Erase (controlled by FLTCTL_ERASE_SECTADDR)
503 SectorEraseControlledByFLTCTL_ERASE_SECTADDR = 0,
504 /// Mass Erase (includes all Main and Information memory sectors that don't have cor
505 MODE_1 = 1
506 ],
507 /// Type of memory that erase operation is carried out on
508 TYPE OFFSET(2) NUMBITS(2) [
509 /// Main Memory
510 MainMemory = 0,
511 /// Information Memory
512 InformationMemory = 1,
513 /// Engineering Memory
514 EngineeringMemory = 3
515 ],
516 /// Status of erase operations in the Flash memory
517 STATUS OFFSET(16) NUMBITS(2) [
518 /// Idle (no program operation currently active)
519 IdleNoProgramOperationCurrentlyActive = 0,
520 /// Erase operation triggered to START but pending
521 EraseOperationTriggeredToSTARTButPending = 1,
522 /// Erase operation in progress
523 EraseOperationInProgress = 2,
524 /// Erase operation completed (status of completed erase remains in this state unles
525 STATUS_3 = 3
526 ],
527 /// Erase Operation was terminated due to attempted erase of reserved memory address
528 ADDR_ERR OFFSET(18) NUMBITS(1) [],
529 /// Clear status bits 18-16 of this register
530 CLR_STAT OFFSET(19) NUMBITS(1) []
531 ],
532 FLCTL_BANK0_INFO_WEPROT [
533 /// Protects Sector 0 from program or erase
534 PROT0 OFFSET(0) NUMBITS(1) [],
535 /// Protects Sector 1 from program or erase
536 PROT1 OFFSET(1) NUMBITS(1) []
537 ],
538 FLCTL_BANK0_MAIN_WEPROT [
539 /// Protects Sector 0 from program or erase
540 PROT0 OFFSET(0) NUMBITS(1) [],
541 /// Protects Sector 1 from program or erase
542 PROT1 OFFSET(1) NUMBITS(1) [],
543 /// Protects Sector 2 from program or erase
544 PROT2 OFFSET(2) NUMBITS(1) [],
545 /// Protects Sector 3 from program or erase
546 PROT3 OFFSET(3) NUMBITS(1) [],
547 /// Protects Sector 4 from program or erase
548 PROT4 OFFSET(4) NUMBITS(1) [],
549 /// Protects Sector 5 from program or erase
550 PROT5 OFFSET(5) NUMBITS(1) [],
551 /// Protects Sector 6 from program or erase
552 PROT6 OFFSET(6) NUMBITS(1) [],
553 /// Protects Sector 7 from program or erase
554 PROT7 OFFSET(7) NUMBITS(1) [],
555 /// Protects Sector 8 from program or erase
556 PROT8 OFFSET(8) NUMBITS(1) [],
557 /// Protects Sector 9 from program or erase
558 PROT9 OFFSET(9) NUMBITS(1) [],
559 /// Protects Sector 10 from program or erase
560 PROT10 OFFSET(10) NUMBITS(1) [],
561 /// Protects Sector 11 from program or erase
562 PROT11 OFFSET(11) NUMBITS(1) [],
563 /// Protects Sector 12 from program or erase
564 PROT12 OFFSET(12) NUMBITS(1) [],
565 /// Protects Sector 13 from program or erase
566 PROT13 OFFSET(13) NUMBITS(1) [],
567 /// Protects Sector 14 from program or erase
568 PROT14 OFFSET(14) NUMBITS(1) [],
569 /// Protects Sector 15 from program or erase
570 PROT15 OFFSET(15) NUMBITS(1) [],
571 /// Protects Sector 16 from program or erase
572 PROT16 OFFSET(16) NUMBITS(1) [],
573 /// Protects Sector 17 from program or erase
574 PROT17 OFFSET(17) NUMBITS(1) [],
575 /// Protects Sector 18 from program or erase
576 PROT18 OFFSET(18) NUMBITS(1) [],
577 /// Protects Sector 19 from program or erase
578 PROT19 OFFSET(19) NUMBITS(1) [],
579 /// Protects Sector 20 from program or erase
580 PROT20 OFFSET(20) NUMBITS(1) [],
581 /// Protects Sector 21 from program or erase
582 PROT21 OFFSET(21) NUMBITS(1) [],
583 /// Protects Sector 22 from program or erase
584 PROT22 OFFSET(22) NUMBITS(1) [],
585 /// Protects Sector 23 from program or erase
586 PROT23 OFFSET(23) NUMBITS(1) [],
587 /// Protects Sector 24 from program or erase
588 PROT24 OFFSET(24) NUMBITS(1) [],
589 /// Protects Sector 25 from program or erase
590 PROT25 OFFSET(25) NUMBITS(1) [],
591 /// Protects Sector 26 from program or erase
592 PROT26 OFFSET(26) NUMBITS(1) [],
593 /// Protects Sector 27 from program or erase
594 PROT27 OFFSET(27) NUMBITS(1) [],
595 /// Protects Sector 28 from program or erase
596 PROT28 OFFSET(28) NUMBITS(1) [],
597 /// Protects Sector 29 from program or erase
598 PROT29 OFFSET(29) NUMBITS(1) [],
599 /// Protects Sector 30 from program or erase
600 PROT30 OFFSET(30) NUMBITS(1) [],
601 /// Protects Sector 31 from program or erase
602 PROT31 OFFSET(31) NUMBITS(1) []
603 ],
604 FLCTL_BANK1_INFO_WEPROT [
605 /// Protects Sector 0 from program or erase operations
606 PROT0 OFFSET(0) NUMBITS(1) [],
607 /// Protects Sector 1 from program or erase operations
608 PROT1 OFFSET(1) NUMBITS(1) []
609 ],
610 FLCTL_BANK1_MAIN_WEPROT [
611 /// Protects Sector 0 from program or erase operations
612 PROT0 OFFSET(0) NUMBITS(1) [],
613 /// Protects Sector 1 from program or erase operations
614 PROT1 OFFSET(1) NUMBITS(1) [],
615 /// Protects Sector 2 from program or erase operations
616 PROT2 OFFSET(2) NUMBITS(1) [],
617 /// Protects Sector 3 from program or erase operations
618 PROT3 OFFSET(3) NUMBITS(1) [],
619 /// Protects Sector 4 from program or erase operations
620 PROT4 OFFSET(4) NUMBITS(1) [],
621 /// Protects Sector 5 from program or erase operations
622 PROT5 OFFSET(5) NUMBITS(1) [],
623 /// Protects Sector 6 from program or erase operations
624 PROT6 OFFSET(6) NUMBITS(1) [],
625 /// Protects Sector 7 from program or erase operations
626 PROT7 OFFSET(7) NUMBITS(1) [],
627 /// Protects Sector 8 from program or erase operations
628 PROT8 OFFSET(8) NUMBITS(1) [],
629 /// Protects Sector 9 from program or erase operations
630 PROT9 OFFSET(9) NUMBITS(1) [],
631 /// Protects Sector 10 from program or erase operations
632 PROT10 OFFSET(10) NUMBITS(1) [],
633 /// Protects Sector 11 from program or erase operations
634 PROT11 OFFSET(11) NUMBITS(1) [],
635 /// Protects Sector 12 from program or erase operations
636 PROT12 OFFSET(12) NUMBITS(1) [],
637 /// Protects Sector 13 from program or erase operations
638 PROT13 OFFSET(13) NUMBITS(1) [],
639 /// Protects Sector 14 from program or erase operations
640 PROT14 OFFSET(14) NUMBITS(1) [],
641 /// Protects Sector 15 from program or erase operations
642 PROT15 OFFSET(15) NUMBITS(1) [],
643 /// Protects Sector 16 from program or erase operations
644 PROT16 OFFSET(16) NUMBITS(1) [],
645 /// Protects Sector 17 from program or erase operations
646 PROT17 OFFSET(17) NUMBITS(1) [],
647 /// Protects Sector 18 from program or erase operations
648 PROT18 OFFSET(18) NUMBITS(1) [],
649 /// Protects Sector 19 from program or erase operations
650 PROT19 OFFSET(19) NUMBITS(1) [],
651 /// Protects Sector 20 from program or erase operations
652 PROT20 OFFSET(20) NUMBITS(1) [],
653 /// Protects Sector 21 from program or erase operations
654 PROT21 OFFSET(21) NUMBITS(1) [],
655 /// Protects Sector 22 from program or erase operations
656 PROT22 OFFSET(22) NUMBITS(1) [],
657 /// Protects Sector 23 from program or erase operations
658 PROT23 OFFSET(23) NUMBITS(1) [],
659 /// Protects Sector 24 from program or erase operations
660 PROT24 OFFSET(24) NUMBITS(1) [],
661 /// Protects Sector 25 from program or erase operations
662 PROT25 OFFSET(25) NUMBITS(1) [],
663 /// Protects Sector 26 from program or erase operations
664 PROT26 OFFSET(26) NUMBITS(1) [],
665 /// Protects Sector 27 from program or erase operations
666 PROT27 OFFSET(27) NUMBITS(1) [],
667 /// Protects Sector 28 from program or erase operations
668 PROT28 OFFSET(28) NUMBITS(1) [],
669 /// Protects Sector 29 from program or erase operations
670 PROT29 OFFSET(29) NUMBITS(1) [],
671 /// Protects Sector 30 from program or erase operations
672 PROT30 OFFSET(30) NUMBITS(1) [],
673 /// Protects Sector 31 from program or erase operations
674 PROT31 OFFSET(31) NUMBITS(1) []
675 ],
676 FLCTL_BMRK_CTLSTAT [
677 /// When 1, increments the Instruction Benchmark count register on each instruction
678 I_BMRK OFFSET(0) NUMBITS(1) [],
679 /// When 1, increments the Data Benchmark count register on each data read access to
680 D_BMRK OFFSET(1) NUMBITS(1) [],
681 /// When 1, enables comparison of the Instruction or Data Benchmark Registers agains
682 CMP_EN OFFSET(2) NUMBITS(1) [],
683 /// Selects which benchmark register should be compared against the threshold
684 CMP_SEL OFFSET(3) NUMBITS(1) [
685 /// Compares the Instruction Benchmark Register against the threshold value
686 ComparesTheInstructionBenchmarkRegisterAgainstTheThresholdValue = 0,
687 /// Compares the Data Benchmark Register against the threshold value
688 ComparesTheDataBenchmarkRegisterAgainstTheThresholdValue = 1
689 ]
690 ],
691 FLCTL_IFG [
692 /// If set to 1, indicates that the Read Burst/Compare operation is complete
693 RDBRST OFFSET(0) NUMBITS(1) [],
694 /// If set to 1, indicates that the pre-program verify operation has detected an err
695 AVPRE OFFSET(1) NUMBITS(1) [],
696 /// If set to 1, indicates that the post-program verify operation has failed compari
697 AVPST OFFSET(2) NUMBITS(1) [],
698 /// If set to 1, indicates that a word Program operation is complete
699 PRG OFFSET(3) NUMBITS(1) [],
700 /// If set to 1, indicates that the configured Burst Program operation is complete
701 PRGB OFFSET(4) NUMBITS(1) [],
702 /// If set to 1, indicates that the Erase operation is complete
703 ERASE OFFSET(5) NUMBITS(1) [],
704 /// If set to 1, indicates that a Benchmark Compare match occurred
705 BMRK OFFSET(8) NUMBITS(1) [],
706 /// If set to 1, indicates a word composition error in full word write mode (possibl
707 PRG_ERR OFFSET(9) NUMBITS(1) []
708 ],
709 FLCTL_IE [
710 /// If set to 1, enables the Controller to generate an interrupt based on the corres
711 RDBRST OFFSET(0) NUMBITS(1) [],
712 /// If set to 1, enables the Controller to generate an interrupt based on the corres
713 AVPRE OFFSET(1) NUMBITS(1) [],
714 /// If set to 1, enables the Controller to generate an interrupt based on the corres
715 AVPST OFFSET(2) NUMBITS(1) [],
716 /// If set to 1, enables the Controller to generate an interrupt based on the corres
717 PRG OFFSET(3) NUMBITS(1) [],
718 /// If set to 1, enables the Controller to generate an interrupt based on the corres
719 PRGB OFFSET(4) NUMBITS(1) [],
720 /// If set to 1, enables the Controller to generate an interrupt based on the corres
721 ERASE OFFSET(5) NUMBITS(1) [],
722 /// If set to 1, enables the Controller to generate an interrupt based on the corres
723 BMRK OFFSET(8) NUMBITS(1) [],
724 /// If set to 1, enables the Controller to generate an interrupt based on the corres
725 PRG_ERR OFFSET(9) NUMBITS(1) []
726 ],
727 FLCTL_CLRIFG [
728 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
729 RDBRST OFFSET(0) NUMBITS(1) [],
730 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
731 AVPRE OFFSET(1) NUMBITS(1) [],
732 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
733 AVPST OFFSET(2) NUMBITS(1) [],
734 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
735 PRG OFFSET(3) NUMBITS(1) [],
736 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
737 PRGB OFFSET(4) NUMBITS(1) [],
738 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
739 ERASE OFFSET(5) NUMBITS(1) [],
740 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
741 BMRK OFFSET(8) NUMBITS(1) [],
742 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
743 PRG_ERR OFFSET(9) NUMBITS(1) []
744 ],
745 FLCTL_SETIFG [
746 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
747 RDBRST OFFSET(0) NUMBITS(1) [],
748 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
749 AVPRE OFFSET(1) NUMBITS(1) [],
750 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
751 AVPST OFFSET(2) NUMBITS(1) [],
752 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
753 PRG OFFSET(3) NUMBITS(1) [],
754 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
755 PRGB OFFSET(4) NUMBITS(1) [],
756 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
757 ERASE OFFSET(5) NUMBITS(1) [],
758 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
759 BMRK OFFSET(8) NUMBITS(1) [],
760 /// Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG
761 PRG_ERR OFFSET(9) NUMBITS(1) []
762 ],
763 FLCTL_READ_TIMCTL [
764 /// Configures the length of the Setup phase for this operation
765 SETUP OFFSET(0) NUMBITS(8) [],
766 /// Length of the IREF_BOOST1 signal of the IP
767 IREF_BOOST1 OFFSET(12) NUMBITS(4) [],
768 /// Length of the Setup time into read mode when the device is recovering from one o
769 SETUP_LONG OFFSET(16) NUMBITS(8) []
770 ],
771 FLCTL_PRGVER_TIMCTL [
772 /// Length of the Setup phase for this operation
773 SETUP OFFSET(0) NUMBITS(8) [],
774 /// Length of the Active phase for this operation
775 ACTIVE OFFSET(8) NUMBITS(4) [],
776 /// Length of the Hold phase for this operation
777 HOLD OFFSET(12) NUMBITS(4) []
778 ],
779 FLCTL_PROGRAM_TIMCTL [
780 /// Length of the Setup phase for this operation
781 SETUP OFFSET(0) NUMBITS(8) [],
782 /// Length of the Active phase for this operation
783 ACTIVE OFFSET(8) NUMBITS(20) [],
784 /// Length of the Hold phase for this operation
785 HOLD OFFSET(28) NUMBITS(4) []
786 ],
787 FLCTL_ERASE_TIMCTL [
788 /// Length of the Setup phase for this operation
789 SETUP OFFSET(0) NUMBITS(8) [],
790 /// Length of the Active phase for this operation
791 ACTIVE OFFSET(8) NUMBITS(20) [],
792 /// Length of the Hold phase for this operation
793 HOLD OFFSET(28) NUMBITS(4) []
794 ],
795 FLCTL_MASSERASE_TIMCTL [
796 /// Length of the time for which LDO Boost Signal is kept active
797 BOOST_ACTIVE OFFSET(0) NUMBITS(8) [],
798 /// Length for which Flash deactivates the LDO Boost signal before processing any ne
799 BOOST_HOLD OFFSET(8) NUMBITS(8) []
800 ]
801];
802
803/// Wait states.
804///
805/// If the clock runs with a higher frequency than the flash is able to operate, it's possible to
806/// configure a certain amount of wait-states which stall the CPU in order to access the data within
807/// the flash in a reliable way.
808/// For a detailed description check the datasheet at page 458 section 9.2.2.1.
809#[repr(u32)]
810#[derive(Copy, Clone)]
811pub enum WaitStates {
812 _0 = 0,
813 _1 = 1,
814 _2 = 2,
815 _3 = 3,
816 _4 = 4,
817 _5 = 5,
818 _6 = 6,
819 _7 = 7,
820 _8 = 8,
821 _9 = 9,
822 _10 = 10,
823 _11 = 11,
824 _12 = 12,
825 _13 = 13,
826 _14 = 14,
827 _15 = 15,
828}
829
830pub struct FlCtl {
831 registers: StaticRef<FlCtlRegisters>,
832}
833
834impl FlCtl {
835 pub const fn new() -> FlCtl {
836 FlCtl {
837 registers: FLCTL_BASE,
838 }
839 }
840
841 pub fn set_waitstates(&self, ws: WaitStates) {
842 self.registers
843 .bank0_rdctl
844 .modify(FLCTL_BANK0_RDCTL::WAIT.val(ws as u32));
845 self.registers
846 .bank1_rdctl
847 .modify(FLCTL_BANK1_RDCTL::WAIT.val(ws as u32));
848 }
849
850 pub fn set_buffering(&self, enable: bool) {
851 self.registers.bank0_rdctl.modify(
852 FLCTL_BANK0_RDCTL::BUFD.val(enable as u32) + FLCTL_BANK0_RDCTL::BUFI.val(enable as u32),
853 );
854 self.registers.bank1_rdctl.modify(
855 FLCTL_BANK1_RDCTL::BUFD.val(enable as u32) + FLCTL_BANK1_RDCTL::BUFI.val(enable as u32),
856 );
857 }
858}