cortexm3/
lib.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Shared implementations for ARM Cortex-M3 MCUs.
6
7#![crate_name = "cortexm3"]
8#![crate_type = "rlib"]
9#![no_std]
10
11use core::fmt::Write;
12
13pub mod mpu {
14    pub type MPU = cortexm::mpu::MPU<8, 32>;
15}
16
17pub use cortexm::initialize_ram_jump_to_main;
18pub use cortexm::interrupt_mask;
19pub use cortexm::nvic;
20pub use cortexm::scb;
21pub use cortexm::support;
22pub use cortexm::systick;
23pub use cortexm::unhandled_interrupt;
24pub use cortexm::CortexMVariant;
25
26// Enum with no variants to ensure that this type is not instantiable. It is
27// only used to pass architecture-specific constants and functions via the
28// `CortexMVariant` trait.
29pub enum CortexM3 {}
30
31impl cortexm::CortexMVariant for CortexM3 {
32    const GENERIC_ISR: unsafe extern "C" fn() = cortexv7m::generic_isr_arm_v7m;
33    const SYSTICK_HANDLER: unsafe extern "C" fn() = cortexv7m::systick_handler_arm_v7m;
34    const SVC_HANDLER: unsafe extern "C" fn() = cortexv7m::svc_handler_arm_v7m;
35    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = cortexv7m::hard_fault_handler_arm_v7m;
36
37    #[cfg(all(target_arch = "arm", target_os = "none"))]
38    unsafe fn switch_to_user(
39        user_stack: *const usize,
40        process_regs: &mut [usize; 8],
41    ) -> *const usize {
42        cortexv7m::switch_to_user_arm_v7m(user_stack, process_regs)
43    }
44
45    #[cfg(not(all(target_arch = "arm", target_os = "none")))]
46    unsafe fn switch_to_user(
47        _user_stack: *const usize,
48        _process_regs: &mut [usize; 8],
49    ) -> *const usize {
50        unimplemented!()
51    }
52
53    #[inline]
54    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
55        cortexm::print_cortexm_state(writer)
56    }
57}
58
59pub mod syscall {
60    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM3>;
61}