cortexm0p/
lib.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Shared implementations for ARM Cortex-M0+ MCUs.
6
7#![no_std]
8
9use core::fmt::Write;
10
11pub mod mpu {
12    use kernel::utilities::StaticRef;
13
14    pub type MPU = cortexm::mpu::MPU<8, 256>;
15
16    const MPU_BASE_ADDRESS: StaticRef<cortexm::mpu::MpuRegisters> =
17        unsafe { StaticRef::new(0xE000ED90 as *const cortexm::mpu::MpuRegisters) };
18
19    pub unsafe fn new() -> MPU {
20        MPU::new(MPU_BASE_ADDRESS)
21    }
22}
23
24// Re-export the base generic cortex-m functions here as they are
25// valid on cortex-m0.
26pub use cortexm::support;
27
28pub use cortexm::initialize_ram_jump_to_main;
29pub use cortexm::interrupt_mask;
30pub use cortexm::nvic;
31pub use cortexm::scb;
32pub use cortexm::systick;
33pub use cortexm::unhandled_interrupt;
34pub use cortexm::CortexMVariant;
35use cortexm0::CortexM0;
36
37// Mock implementation for tests on Travis-CI.
38#[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
39pub unsafe extern "C" fn svc_handler() {
40    unimplemented!()
41}
42
43#[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
44#[unsafe(naked)]
45pub unsafe extern "C" fn svc_handler() {
46    use core::arch::naked_asm;
47    naked_asm!(
48        "
49  ldr r0, 100f // EXC_RETURN_MSP
50  cmp lr, r0
51  bne 300f // to_kernel
52
53  // If we get here, then this is a context switch from the kernel to the
54  // application. Set thread mode to unprivileged to run the application.
55  movs r0, #1
56  msr CONTROL, r0
57  ldr r1, 200f // EXC_RETURN_PSP
58  bx r1
59
60300: // to_kernel
61  ldr r0, =SYSCALL_FIRED
62  movs r1, #1
63  str r1, [r0, #0]
64  // Set thread mode to privileged as we switch back to the kernel.
65  movs r0, #0
66  msr CONTROL, r0
67  ldr r1, 100f // EXC_RETURN_MSP
68  bx r1
69
70.align 4
71100: // EXC_RETURN_MSP
72  .word 0xFFFFFFF9
73200: // EXC_RETURN_PSP
74  .word 0xFFFFFFFD
75  ",
76    );
77}
78
79// Enum with no variants to ensure that this type is not instantiable. It is
80// only used to pass architecture-specific constants and functions via the
81// `CortexMVariant` trait.
82pub enum CortexM0P {}
83
84impl cortexm::CortexMVariant for CortexM0P {
85    const GENERIC_ISR: unsafe extern "C" fn() = CortexM0::GENERIC_ISR;
86    const SYSTICK_HANDLER: unsafe extern "C" fn() = CortexM0::SYSTICK_HANDLER;
87    const SVC_HANDLER: unsafe extern "C" fn() = svc_handler;
88    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = CortexM0::HARD_FAULT_HANDLER;
89
90    #[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
91    unsafe fn switch_to_user(
92        user_stack: *const usize,
93        process_regs: &mut [usize; 8],
94    ) -> *const usize {
95        CortexM0::switch_to_user(user_stack, process_regs)
96    }
97
98    #[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
99    unsafe fn switch_to_user(
100        _user_stack: *const usize,
101        _process_regs: &mut [usize; 8],
102    ) -> *const usize {
103        unimplemented!()
104    }
105
106    #[inline]
107    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
108        cortexm::print_cortexm_state(writer)
109    }
110}
111
112pub mod syscall {
113    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM0P>;
114}