cortexm0p/
lib.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Shared implementations for ARM Cortex-M0+ MCUs.
6
7#![crate_name = "cortexm0p"]
8#![crate_type = "rlib"]
9#![no_std]
10
11use core::fmt::Write;
12
13pub mod mpu {
14    pub type MPU = cortexm::mpu::MPU<8, 256>;
15}
16
17// Re-export the base generic cortex-m functions here as they are
18// valid on cortex-m0.
19pub use cortexm::support;
20
21pub use cortexm::initialize_ram_jump_to_main;
22pub use cortexm::interrupt_mask;
23pub use cortexm::nvic;
24pub use cortexm::scb;
25pub use cortexm::systick;
26pub use cortexm::unhandled_interrupt;
27pub use cortexm::CortexMVariant;
28use cortexm0::CortexM0;
29
30// Mock implementation for tests on Travis-CI.
31#[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
32pub unsafe extern "C" fn svc_handler_m0p() {
33    unimplemented!()
34}
35
36#[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
37extern "C" {
38    pub fn svc_handler_m0p();
39}
40
41#[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
42core::arch::global_asm!(
43    "
44  .section .svc_handler_m0p, \"ax\"
45  .global svc_handler_m0p
46  .thumb_func
47svc_handler_m0p:
48  ldr r0, 100f // EXC_RETURN_MSP
49  cmp lr, r0
50  bne 300f // to_kernel
51
52  // If we get here, then this is a context switch from the kernel to the
53  // application. Set thread mode to unprivileged to run the application.
54  movs r0, #1
55  msr CONTROL, r0
56  ldr r1, 200f // EXC_RETURN_PSP
57  bx r1
58
59300: // to_kernel
60  ldr r0, =SYSCALL_FIRED
61  movs r1, #1
62  str r1, [r0, #0]
63  // Set thread mode to privileged as we switch back to the kernel.
64  movs r0, #0
65  msr CONTROL, r0
66  ldr r1, 100f // EXC_RETURN_MSP
67  bx r1
68
69.align 4
70100: // EXC_RETURN_MSP
71  .word 0xFFFFFFF9
72200: // EXC_RETURN_PSP
73  .word 0xFFFFFFFD
74  "
75);
76
77// Enum with no variants to ensure that this type is not instantiable. It is
78// only used to pass architecture-specific constants and functions via the
79// `CortexMVariant` trait.
80pub enum CortexM0P {}
81
82impl cortexm::CortexMVariant for CortexM0P {
83    const GENERIC_ISR: unsafe extern "C" fn() = CortexM0::GENERIC_ISR;
84    const SYSTICK_HANDLER: unsafe extern "C" fn() = CortexM0::SYSTICK_HANDLER;
85    const SVC_HANDLER: unsafe extern "C" fn() = svc_handler_m0p;
86    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = CortexM0::HARD_FAULT_HANDLER;
87
88    #[cfg(any(doc, all(target_arch = "arm", target_os = "none")))]
89    unsafe fn switch_to_user(
90        user_stack: *const usize,
91        process_regs: &mut [usize; 8],
92    ) -> *const usize {
93        CortexM0::switch_to_user(user_stack, process_regs)
94    }
95
96    #[cfg(not(any(doc, all(target_arch = "arm", target_os = "none"))))]
97    unsafe fn switch_to_user(
98        _user_stack: *const usize,
99        _process_regs: &mut [usize; 8],
100    ) -> *const usize {
101        unimplemented!()
102    }
103
104    #[inline]
105    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
106        cortexm::print_cortexm_state(writer)
107    }
108}
109
110pub mod syscall {
111    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM0P>;
112}
cortexm0p/lib.rs

cortexm0p/
lib.rs
