capsules_extra/
rf233_const.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Support for the RF233 capsule
6
7#![allow(non_camel_case_types)]
8
9#[derive(PartialEq, Copy, Clone, Debug)]
10pub enum RF233Register {
11    MIN = 0x00,
12    TRX_STATUS = 0x01,
13    TRX_STATE = 0x02,
14    TRX_CTRL_0 = 0x03,
15    TRX_CTRL_1 = 0x04,
16    PHY_TX_PWR = 0x05,
17    PHY_RSSI = 0x06,
18    PHY_ED_LEVEL = 0x07,
19    PHY_CC_CCA = 0x08,
20    CCA_THRES = 0x09,
21    RX_CTRL = 0x0A,
22    SFD_VALUE = 0x0B,
23    TRX_CTRL_2 = 0x0C,
24    ANT_DIV = 0x0D,
25    IRQ_MASK = 0x0E,
26    IRQ_STATUS = 0x0F,
27    VCTRL = 0x10,
28    BATMON = 0x11,
29    XOSC_CTRL = 0x12,
30    CC_CTRL_0 = 0x13,
31    CC_CTRL_1 = 0x14,
32    RX_SYN = 0x15,
33    TRX_RPC = 0x16,
34    XAH_CTRL_1 = 0x17,
35    FTN_CTRL = 0x18,
36    XAH_CTRL_2 = 0x19,
37    PLL_CF = 0x1A,
38    PLL_DCU = 0x1B,
39    PART_NUM = 0x1C,
40    VERSION_NUM = 0x1D,
41    MAN_ID_0 = 0x1E,
42    MAN_ID_1 = 0x1F,
43    SHORT_ADDR_0 = 0x20,
44    SHORT_ADDR_1 = 0x21,
45    PAN_ID_0 = 0x22,
46    PAN_ID_1 = 0x23,
47    IEEE_ADDR_0 = 0x24,
48    IEEE_ADDR_1 = 0x25,
49    IEEE_ADDR_2 = 0x26,
50    IEEE_ADDR_3 = 0x27,
51    IEEE_ADDR_4 = 0x28,
52    IEEE_ADDR_5 = 0x29,
53    IEEE_ADDR_6 = 0x2A,
54    IEEE_ADDR_7 = 0x2B,
55    XAH_CTRL_0 = 0x2C,
56    CSMA_SEED_0 = 0x2D,
57    CSMA_SEED_1 = 0x2E,
58    CSMA_BE = 0x2F,
59    TST_CTRL_DIGI = 0x36,
60    PHY_TX_TIME = 0x3B,
61    TST_AGC = 0x3C,
62    TST_SDM = 0x3D,
63    MAX = 0x3E,
64}
65
66// These are particular flags of different registers.
67pub const TRX_CTRL_1_DIG34_RXTX_INDICATOR: u8 = 1 << 7;
68pub const TRX_CTRL_1_SPI_CMD_TRX_STATUS: u8 = 1 << 2;
69pub const TRX_CTRL_1_AUTO_CRC: u8 = 1 << 5;
70pub const PHY_TX_PWR_4: u8 = 0;
71pub const PHY_CC_CCA_MODE_CS_OR_ED: u8 = 0 << 5;
72pub const PHY_CC_CCA_MODE_ED: u8 = 1 << 5;
73pub const PHY_CC_CCA_MODE_CS: u8 = 2 << 5;
74pub const PHY_CC_CCA_MODE_CS_AND_ED: u8 = 3 << 5;
75pub const PHY_RSSI_RX_CRC_VALID: u8 = 1 << 7;
76pub const TRX_CTRL_2_RX_SAFE_MODE: u8 = 1 << 7;
77pub const TRX_CTRL_2_DATA_RATE_250: u8 = 0;
78pub const IRQ_TRXBUF_ACCESS_VIOLATION: u8 = 1 << 6;
79pub const IRQ_TRX_DONE: u8 = 1 << 3;
80pub const IRQ_RX_START: u8 = 1 << 2;
81pub const IRQ_PLL_LOCK: u8 = 1 << 0;
82pub const XAH_CTRL_1_AACK_PROM_MODE: u8 = 1 << 1;
83pub const XAH_CTRL_1_AACK_UPLD_RES_FT: u8 = 1 << 4;
84pub const XAH_CTRL_1_AACK_FLTR_RES_FT: u8 = 1 << 5;
85pub const AACK_FVN_MODE: u8 = 3 << 6;
86
87// Flag combinations that are used in initialization.
88pub const TRX_CTRL_1: u8 =
89    TRX_CTRL_1_DIG34_RXTX_INDICATOR | TRX_CTRL_1_SPI_CMD_TRX_STATUS | TRX_CTRL_1_AUTO_CRC;
90pub const TRX_CTRL_2: u8 = TRX_CTRL_2_RX_SAFE_MODE | TRX_CTRL_2_DATA_RATE_250;
91pub const PHY_CC_CCA: u8 = DEFAULT_PHY_CHANNEL | PHY_CC_CCA_MODE_CS_OR_ED;
92pub const PHY_TX_PWR: u8 = PHY_TX_PWR_4;
93pub const DEFAULT_PHY_CHANNEL: u8 = 26;
94pub const IRQ_MASK: u8 = IRQ_TRXBUF_ACCESS_VIOLATION | IRQ_TRX_DONE | IRQ_PLL_LOCK | IRQ_RX_START;
95pub const XAH_CTRL_1: u8 =
96    XAH_CTRL_1_AACK_UPLD_RES_FT | XAH_CTRL_1_AACK_FLTR_RES_FT | XAH_CTRL_1_AACK_PROM_MODE;
97pub const XAH_CTRL_0: u8 = 0;
98pub const CSMA_SEED_1: u8 = AACK_FVN_MODE;
99pub const TRX_RPC: u8 = 0xFF;
100pub const TRX_TRAC_MASK: u8 = 0xE0;
101pub const TRX_TRAC_SUCCESS_DATA_PENDING: u8 = 1 << 5;
102pub const TRX_TRAC_CHANNEL_ACCESS_FAILURE: u8 = 3 << 5;
103
104// Default address settings.
105pub const PAN_ID_0: u8 = 0x22;
106pub const PAN_ID_1: u8 = 0x22;
107pub const IEEE_ADDR_0: u8 = 0x11;
108pub const IEEE_ADDR_1: u8 = 0x22;
109pub const IEEE_ADDR_2: u8 = 0x33;
110pub const IEEE_ADDR_3: u8 = 0x44;
111pub const IEEE_ADDR_4: u8 = 0x55;
112pub const IEEE_ADDR_5: u8 = 0x66;
113pub const IEEE_ADDR_6: u8 = 0x77;
114pub const IEEE_ADDR_7: u8 = 0x88;
115pub const SHORT_ADDR_0: u8 = 0x11;
116pub const SHORT_ADDR_1: u8 = 0x22;
117
118// Interrupt flags.
119#[repr(u8)]
120pub enum InteruptFlags {
121    IRQ_7_BAT_LOW = 0x80,
122    IRQ_6_TRX_UR = 0x40,
123    IRQ_5_AMI = 0x20,
124    IRQ_4_CCA_ED_DONE = 0x10,
125    IRQ_3_TRX_END = 0x08,
126    IRQ_2_RX_START = 0x04,
127    IRQ_1_PLL_UNLOCK = 0x02,
128    IRQ_0_PLL_LOCK = 0x01,
129}
130
131// The commands issued over SPI (first 2-3 bits).
132#[derive(PartialEq, Copy, Clone, Debug)]
133pub enum RF233BusCommand {
134    REGISTER_READ = 0x80,
135    REGISTER_WRITE = 0xC0,
136    FRAME_READ = 0x20,
137    FRAME_WRITE = 0x60,
138    SRAM_READ = 0x00,
139    SRAM_WRITE = 0x40,
140}
141// The values of the radio's internal state, fetched
142// from SPI operations or TRX_STATUS.
143#[derive(PartialEq, Copy, Clone, Debug)]
144pub enum ExternalState {
145    ON = 0x00,
146    BUSY_RX = 0x01,
147    BUSY_TX = 0x02,
148    RX_ON = 0x06,
149    TRX_OFF = 0x08,
150    PLL_ON = 0x09,
151    SLEEP = 0x0F,
152    PREP_DEEP_SLEEP = 0x10,
153    BUSY_RX_AACK = 0x11,
154    BUSY_TX_ARET = 0x12,
155    RX_AACK_ON = 0x16,
156    TX_ARET_ON = 0x19,
157    STATE_TRANSITION_IN_PROGRESS = 0x1F,
158}
159
160// Some of the values written in TRX_STATE to change
161// radio state.
162pub enum RF233TrxCmd {
163    TX_START = 0x02,
164    RX_ON = 0x06,
165    OFF = 0x08,
166    PLL_ON = 0x09,
167    RX_AACK_ON = 0x16,
168    TX_ARET_ON = 0x19,
169}
capsules_extra/rf233_const.rs

capsules_extra/
rf233_const.rs
