riscv/csr/
mseccfg.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use kernel::utilities::registers::register_bitfields;
6
7// Default to 32 bit if compiling for debug/testing.
8#[cfg(not(target_arch = "riscv64"))]
9register_bitfields![usize,
10    pub mseccfg [
11        mml OFFSET(0) NUMBITS(1) [],
12        mmwp OFFSET(1) NUMBITS(1) [],
13        rlb OFFSET(2) NUMBITS(1) [],
14    ]
15];
16
17#[cfg(not(target_arch = "riscv64"))]
18register_bitfields![usize,
19    pub mseccfgh [
20        // This isn't a real entry, it just avoids compilation errors
21        none OFFSET(0) NUMBITS(1) [],
22    ]
23];
24
25#[cfg(target_arch = "riscv64")]
26register_bitfields![usize,
27    pub mseccfg [
28        mml OFFSET(0) NUMBITS(1) [],
29        mmwp OFFSET(1) NUMBITS(1) [],
30        rlb OFFSET(2) NUMBITS(1) [],
31    ]
32];