riscv/csr/
mcycle.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use kernel::utilities::registers::register_bitfields;
6
7// mcycle is the lower XLEN bits of the number of elapsed cycles
8register_bitfields![usize,
9    pub mcycle [
10        mcycle OFFSET(0) NUMBITS(crate::XLEN) []
11    ]
12];
13
14// `mcycleh` is the higher XLEN bits of the number of elapsed cycles.
15// It does not exist on riscv64.
16#[cfg(not(target_arch = "riscv64"))]
17register_bitfields![usize,
18    pub mcycleh [
19        mcycleh OFFSET(0) NUMBITS(crate::XLEN) []
20    ]
21];