msp432/usci.rs
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! (enhanced) Universal Serial Communication Interface (USCI)
6
7use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
8use kernel::utilities::StaticRef;
9
10pub const USCI_A0_BASE: StaticRef<UsciARegisters> =
11 unsafe { StaticRef::new(0x4000_1000 as *const UsciARegisters) };
12#[allow(dead_code)]
13pub const USCI_A1_BASE: StaticRef<UsciARegisters> =
14 unsafe { StaticRef::new(0x4000_1400 as *const UsciARegisters) };
15#[allow(dead_code)]
16pub const USCI_A2_BASE: StaticRef<UsciARegisters> =
17 unsafe { StaticRef::new(0x4000_1800 as *const UsciARegisters) };
18#[allow(dead_code)]
19pub const USCI_A3_BASE: StaticRef<UsciARegisters> =
20 unsafe { StaticRef::new(0x4000_1C00 as *const UsciARegisters) };
21#[allow(dead_code)]
22pub const USCI_B0_BASE: StaticRef<UsciBRegisters> =
23 unsafe { StaticRef::new(0x4000_2000 as *const UsciBRegisters) };
24#[allow(dead_code)]
25pub const USCI_B1_BASE: StaticRef<UsciBRegisters> =
26 unsafe { StaticRef::new(0x4000_2400 as *const UsciBRegisters) };
27#[allow(dead_code)]
28pub const USCI_B2_BASE: StaticRef<UsciBRegisters> =
29 unsafe { StaticRef::new(0x4000_2800 as *const UsciBRegisters) };
30#[allow(dead_code)]
31pub const USCI_B3_BASE: StaticRef<UsciBRegisters> =
32 unsafe { StaticRef::new(0x4000_2C00 as *const UsciBRegisters) };
33
34register_structs! {
35 /// EUSCI_Ax
36 pub UsciARegisters {
37 /// eUSCI_Ax Control Word Register 0
38 (0x00 => pub(crate) ctlw0: ReadWrite<u16, UCAxCTLW0::Register>),
39 /// eUSCI_Ax Control Word Register 1
40 (0x02 => pub(crate) ctlw1: ReadWrite<u16>),
41 (0x04 => _reserved0),
42 /// eUSCI_Ax Baud Rate Control Word Register
43 (0x06 => pub(crate) brw: ReadWrite<u16>),
44 /// eUSCI_Ax Modulation Control Word Register
45 (0x08 => pub(crate) mctlw: ReadWrite<u16, UCAxMCTLW::Register>),
46 /// eUSCI_Ax Status Register
47 (0x0A => pub(crate) statw: ReadWrite<u16, UCAxSTATW::Register>),
48 /// eUSCI_Ax Receive Buffer Register
49 (0x0C => pub(crate) rxbuf: ReadOnly<u16>),
50 /// eUSCI_Ax Transmit Buffer Register
51 (0x0E => pub(crate) txbuf: ReadWrite<u16>),
52 /// eUSCI_Ax Auto Baud Rate Control Register
53 (0x10 => pub(crate) abctl: ReadWrite<u16, UCAxABCTL::Register>),
54 /// eUSCI_Ax IrDA Control Word Register
55 (0x12 => pub(crate) irctl: ReadWrite<u16, UCAxIRCTL::Register>),
56 (0x14 => _reserved1),
57 /// eUSCI_Ax Interrupt Enable Register
58 (0x1A => pub(crate) ie: ReadWrite<u16, UCAxIE::Register>),
59 /// eUSCI_Ax Interrupt Flag Register
60 (0x1C => pub(crate) ifg: ReadWrite<u16, UCAxIFG::Register>),
61 /// eUSCI_Ax Interrupt Vector Register
62 (0x1E => pub(crate) iv: ReadOnly<u16>),
63 (0x20 => @END),
64 },
65 /// EUSCI_Bx
66 pub UsciBRegisters {
67 /// eUSCI_Bx Control Word Register 0
68 (0x00 => pub(crate) ctlw0: ReadWrite<u16, UCBxCTLW0::Register>),
69 /// eUSCI_Bx Control Word Register 1
70 (0x02 => pub(crate) ctlw1: ReadWrite<u16, UCBxCTLW1::Register>),
71 (0x04 => _reserved0),
72 /// eUSCI_Bx Baud Rate Control Word Register
73 (0x06 => pub(crate) brw: ReadWrite<u16>),
74 /// eUSCI_Bx Status Register
75 (0x08 => pub(crate) statw: ReadWrite<u16, UCBxSTATW::Register>),
76 /// eUSCI_Bx Byte Counter Threshold Register
77 (0x0A => pub(crate) tbcnt: ReadWrite<u16>),
78 /// eUSCI_Bx Receive Buffer Register
79 (0x0C => pub(crate) rxbuf: ReadOnly<u16>),
80 /// eUSCI_Bx Transmit Buffer Register
81 (0x0E => pub(crate) txbuf: ReadWrite<u16>),
82 (0x10 => _reserved1),
83 /// eUSCI_Bx I2C Own Address 0 Register
84 (0x14 => pub(crate) i2coa0: ReadWrite<u16, UCBxI2COA0::Register>),
85 /// eUSCI_Bx I2C Own Address 1 Register
86 (0x16 => pub(crate) i2coa1: ReadWrite<u16, UCBxI2COA1::Register>),
87 /// eUSCI_Bx I2C Own Address 2 Register
88 (0x18 => pub(crate) i2coa2: ReadWrite<u16, UCBxI2COA2::Register>),
89 /// eUSCI_Bx I2C Own Address 3 Register
90 (0x1A => pub(crate) i2coa3: ReadWrite<u16, UCBxI2COA3::Register>),
91 /// eUSCI_Bx I2C Received Address Register
92 (0x1C => pub(crate) addrx: ReadOnly<u16>),
93 /// eUSCI_Bx I2C Address Mask Register
94 (0x1E => pub(crate) addmask: ReadWrite<u16>),
95 /// eUSCI_Bx I2C Slave Address Register
96 (0x20 => pub(crate) i2csa: ReadWrite<u16>),
97 (0x22 => _reserved2),
98 /// eUSCI_Bx Interrupt Enable Register
99 (0x2A => pub(crate) ie: ReadWrite<u16, UCBxIE::Register>),
100 /// eUSCI_Bx Interrupt Flag Register
101 (0x2C => pub(crate) ifg: ReadWrite<u16, UCBxIFG::Register>),
102 /// eUSCI_Bx Interrupt Vector Register
103 (0x2E => pub(crate) iv: ReadOnly<u16>),
104 (0x30 => @END),
105 }
106}
107
108register_bitfields![u16,
109 pub(crate) UCAxCTLW0 [
110 /// Software reset enable
111 UCSWRST OFFSET(0) NUMBITS(1) [
112 /// Disabled. eUSCI_A reset released for operation
113 DisabledEUSCI_AResetReleasedForOperation = 0,
114 /// Enabled. eUSCI_A logic held in reset state
115 EnabledEUSCI_ALogicHeldInResetState = 1
116 ],
117 /// Transmit break
118 UCTXBRK OFFSET(1) NUMBITS(1) [
119 /// Next frame transmitted is not a break
120 NextFrameTransmittedIsNotABreak = 0,
121 /// Next frame transmitted is a break or a break/synch
122 NextFrameTransmittedIsABreakOrABreakSynch = 1
123 ],
124 /// Transmit address
125 UCTXADDR OFFSET(2) NUMBITS(1) [
126 /// Next frame transmitted is data
127 NextFrameTransmittedIsData = 0,
128 /// Next frame transmitted is an address
129 NextFrameTransmittedIsAnAddress = 1
130 ],
131 /// Dormant
132 UCDORM OFFSET(3) NUMBITS(1) [
133 /// Not dormant. All received characters set UCRXIFG.
134 NotDormantAllReceivedCharactersSetUCRXIFG = 0,
135 /// Dormant. Only characters that are preceded by an idle-line or with address bit s
136 UCDORM_1 = 1
137 ],
138 /// Receive break character interrupt enable
139 UCBRKIE OFFSET(4) NUMBITS(1) [
140 /// Received break characters do not set UCRXIFG
141 ReceivedBreakCharactersDoNotSetUCRXIFG = 0,
142 /// Received break characters set UCRXIFG
143 ReceivedBreakCharactersSetUCRXIFG = 1
144 ],
145 /// Receive erroneous-character interrupt enable
146 UCRXEIE OFFSET(5) NUMBITS(1) [
147 /// Erroneous characters rejected and UCRXIFG is not set
148 ErroneousCharactersRejectedAndUCRXIFGIsNotSet = 0,
149 /// Erroneous characters received set UCRXIFG
150 ErroneousCharactersReceivedSetUCRXIFG = 1
151 ],
152 /// eUSCI_A clock source select
153 UCSSEL OFFSET(6) NUMBITS(2) [
154 /// UCLK
155 UCLK = 0,
156 /// ACLK
157 ACLK = 1,
158 /// SMCLK
159 SMCLK = 2
160 ],
161 /// Synchronous mode enable
162 UCSYNC OFFSET(8) NUMBITS(1) [
163 /// Asynchronous mode
164 AsynchronousMode = 0,
165 /// Synchronous mode
166 SynchronousMode = 1
167 ],
168 /// eUSCI_A mode
169 UCMODE OFFSET(9) NUMBITS(2) [
170 /// UART mode
171 UARTMode = 0,
172 /// Idle-line multiprocessor mode
173 IdleLineMultiprocessorMode = 1,
174 /// Address-bit multiprocessor mode
175 AddressBitMultiprocessorMode = 2,
176 /// UART mode with automatic baud-rate detection
177 UARTModeWithAutomaticBaudRateDetection = 3
178 ],
179 /// Stop bit select
180 UCSPB OFFSET(11) NUMBITS(1) [
181 /// One stop bit
182 OneStopBit = 0,
183 /// Two stop bits
184 TwoStopBits = 1
185 ],
186 /// Character length
187 UC7BIT OFFSET(12) NUMBITS(1) [
188 /// 8-bit data
189 _8BitData = 0,
190 /// 7-bit data
191 _7BitData = 1
192 ],
193 /// MSB first select
194 UCMSB OFFSET(13) NUMBITS(1) [
195 /// LSB first
196 LSBFirst = 0,
197 /// MSB first
198 MSBFirst = 1
199 ],
200 /// Parity select
201 UCPAR OFFSET(14) NUMBITS(1) [
202 /// Odd parity
203 OddParity = 0,
204 /// Even parity
205 EvenParity = 1
206 ],
207 /// Parity enable
208 UCPEN OFFSET(15) NUMBITS(1) [
209 /// Parity disabled
210 ParityDisabled = 0,
211 /// Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In add
212 UCPEN_1 = 1
213 ]
214 ],
215
216 pub(crate) UCAxCTLW1 [
217 /// Deglitch time
218 UCGLIT OFFSET(0) NUMBITS(2) [
219 /// Approximately 5ns
220 _5ns = 0,
221 /// Approximately 20ns
222 _20ns = 1,
223 /// Approximately 30ns
224 _30ns = 2,
225 /// Approximately 50ns
226 _50ns = 3
227 ]
228 ],
229 pub(crate) UCAxMCTLW [
230 /// Oversampling mode enabled
231 UCOS16 OFFSET(0) NUMBITS(1) [
232 /// Disabled
233 Disabled = 0,
234 /// Enabled
235 Enabled = 1
236 ],
237 /// First modulation stage select
238 UCBRF OFFSET(4) NUMBITS(4) [],
239 /// Second modulation stage select
240 UCBRS OFFSET(8) NUMBITS(8) []
241 ],
242 pub(crate) UCAxSTATW [
243 /// eUSCI_A busy
244 UCBUSY OFFSET(0) NUMBITS(1) [
245 /// eUSCI_A inactive
246 EUSCI_AInactive = 0,
247 /// eUSCI_A transmitting or receiving
248 EUSCI_ATransmittingOrReceiving = 1
249 ],
250 /// Address received / Idle line detected
251 UCADDR_UCIDLE OFFSET(1) NUMBITS(1) [],
252 /// Receive error flag
253 UCRXERR OFFSET(2) NUMBITS(1) [
254 /// No receive errors detected
255 NoReceiveErrorsDetected = 0,
256 /// Receive error detected
257 ReceiveErrorDetected = 1
258 ],
259 /// Break detect flag
260 UCBRK OFFSET(3) NUMBITS(1) [
261 /// No break condition
262 NoBreakCondition = 0,
263 /// Break condition occurred
264 BreakConditionOccurred = 1
265 ],
266 /// Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxR
267 UCPE OFFSET(4) NUMBITS(1) [
268 /// No error
269 NoError = 0,
270 /// Character received with parity error
271 CharacterReceivedWithParityError = 1
272 ],
273 /// Overrun error flag
274 UCOE OFFSET(5) NUMBITS(1) [
275 /// No error
276 NoError = 0,
277 /// Overrun error occurred
278 OverrunErrorOccurred = 1
279 ],
280 /// Framing error flag
281 UCFE OFFSET(6) NUMBITS(1) [
282 /// No error
283 NoError = 0,
284 /// Character received with low stop bit
285 CharacterReceivedWithLowStopBit = 1
286 ],
287 /// Listen enable
288 UCLISTEN OFFSET(7) NUMBITS(1) [
289 /// Disabled
290 Disabled = 0,
291 /// Enabled. UCAxTXD is internally fed back to the receiver
292 EnabledUCAxTXDIsInternallyFedBackToTheReceiver = 1
293 ]
294 ],
295 pub(crate) UCAxABCTL [
296 /// Automatic baud-rate detect enable
297 UCABDEN OFFSET(0) NUMBITS(1) [
298 /// Baud-rate detection disabled. Length of break and synch field is not measured.
299 BaudRateDetectionDisabledLengthOfBreakAndSynchFieldIsNotMeasured = 0,
300 /// Baud-rate detection enabled. Length of break and synch field is measured and bau
301 UCABDEN_1 = 1
302 ],
303 /// Break time out error
304 UCBTOE OFFSET(2) NUMBITS(1) [
305 /// No error
306 NoError = 0,
307 /// Length of break field exceeded 22 bit times
308 LengthOfBreakFieldExceeded22BitTimes = 1
309 ],
310 /// Synch field time out error
311 UCSTOE OFFSET(3) NUMBITS(1) [
312 /// No error
313 NoError = 0,
314 /// Length of synch field exceeded measurable time
315 LengthOfSynchFieldExceededMeasurableTime = 1
316 ],
317 /// Break/synch delimiter length
318 UCDELIM OFFSET(4) NUMBITS(2) [
319 /// 1 bit time
320 _1BitTime = 0,
321 /// 2 bit times
322 _2BitTimes = 1,
323 /// 3 bit times
324 _3BitTimes = 2,
325 /// 4 bit times
326 _4BitTimes = 3
327 ]
328 ],
329 pub(crate) UCAxIRCTL [
330 /// IrDA encoder/decoder enable
331 UCIREN OFFSET(0) NUMBITS(1) [
332 /// IrDA encoder/decoder disabled
333 IrDAEncoderDecoderDisabled = 0,
334 /// IrDA encoder/decoder enabled
335 IrDAEncoderDecoderEnabled = 1
336 ],
337 /// IrDA transmit pulse clock select
338 UCIRTXCLK OFFSET(1) NUMBITS(1) [
339 /// BRCLK
340 BRCLK = 0,
341 /// BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.
342 BITCLK16WhenUCOS161OtherwiseBRCLK = 1
343 ],
344 /// Transmit pulse length
345 UCIRTXPL OFFSET(2) NUMBITS(6) [],
346 /// IrDA receive filter enabled
347 UCIRRXFE OFFSET(8) NUMBITS(1) [
348 /// Receive filter disabled
349 ReceiveFilterDisabled = 0,
350 /// Receive filter enabled
351 ReceiveFilterEnabled = 1
352 ],
353 /// IrDA receive input UCAxRXD polarity
354 UCIRRXPL OFFSET(9) NUMBITS(1) [
355 /// IrDA transceiver delivers a high pulse when a light pulse is seen
356 IrDATransceiverDeliversAHighPulseWhenALightPulseIsSeen = 0,
357 /// IrDA transceiver delivers a low pulse when a light pulse is seen
358 IrDATransceiverDeliversALowPulseWhenALightPulseIsSeen = 1
359 ],
360 /// Receive filter length
361 UCIRRXFL OFFSET(10) NUMBITS(4) []
362 ],
363 pub(crate) UCAxIE [
364 /// Receive interrupt enable
365 UCRXIE OFFSET(0) NUMBITS(1) [
366 /// Interrupt disabled
367 InterruptDisabled = 0,
368 /// Interrupt enabled
369 InterruptEnabled = 1
370 ],
371 /// Transmit interrupt enable
372 UCTXIE OFFSET(1) NUMBITS(1) [
373 /// Interrupt disabled
374 InterruptDisabled = 0,
375 /// Interrupt enabled
376 InterruptEnabled = 1
377 ],
378 /// Start bit interrupt enable
379 UCSTTIE OFFSET(2) NUMBITS(1) [
380 /// Interrupt disabled
381 InterruptDisabled = 0,
382 /// Interrupt enabled
383 InterruptEnabled = 1
384 ],
385 /// Transmit complete interrupt enable
386 UCTXCPTIE OFFSET(3) NUMBITS(1) [
387 /// Interrupt disabled
388 InterruptDisabled = 0,
389 /// Interrupt enabled
390 InterruptEnabled = 1
391 ]
392 ],
393 pub(crate) UCAxIFG [
394 /// Receive interrupt flag
395 UCRXIFG OFFSET(0) NUMBITS(1) [
396 /// No interrupt pending
397 NoInterruptPending = 0,
398 /// Interrupt pending
399 InterruptPending = 1
400 ],
401 /// Transmit interrupt flag
402 UCTXIFG OFFSET(1) NUMBITS(1) [
403 /// No interrupt pending
404 NoInterruptPending = 0,
405 /// Interrupt pending
406 InterruptPending = 1
407 ],
408 /// Start bit interrupt flag
409 UCSTTIFG OFFSET(2) NUMBITS(1) [
410 /// No interrupt pending
411 NoInterruptPending = 0,
412 /// Interrupt pending
413 InterruptPending = 1
414 ],
415 /// Transmit ready interrupt enable
416 UCTXCPTIFG OFFSET(3) NUMBITS(1) [
417 /// No interrupt pending
418 NoInterruptPending = 0,
419 /// Interrupt pending
420 InterruptPending = 1
421 ]
422 ],
423 pub(crate) UCAxIV [
424 UCIV OFFSET(0) NUMBITS(16) [
425 NoInterrupt = 0,
426 ReceiveBufferFull = 2,
427 TransmitBufferEmpty = 4,
428 StartBitReceived = 6,
429 TransmitComplete = 8
430 ]
431 ]
432];
433
434register_bitfields![u16,
435 pub(crate) UCBxCTLW0 [
436 /// Software reset enable
437 UCSWRST OFFSET(0) NUMBITS(1) [
438 /// Disabled. eUSCI_B reset released for operation
439 DisabledEUSCI_BResetReleasedForOperation = 0,
440 /// Enabled. eUSCI_B logic held in reset state
441 EnabledEUSCI_BLogicHeldInResetState = 1
442 ],
443 /// Transmit START condition in master mode
444 UCTXSTT OFFSET(1) NUMBITS(1) [
445 /// Do not generate START condition
446 DoNotGenerateSTARTCondition = 0,
447 /// Generate START condition
448 GenerateSTARTCondition = 1
449 ],
450 /// Transmit STOP condition in master mode
451 UCTXSTP OFFSET(2) NUMBITS(1) [
452 /// No STOP generated
453 NoSTOPGenerated = 0,
454 /// Generate STOP
455 GenerateSTOP = 1
456 ],
457 /// Transmit a NACK
458 UCTXNACK OFFSET(3) NUMBITS(1) [
459 /// Acknowledge normally
460 AcknowledgeNormally = 0,
461 /// Generate NACK
462 GenerateNACK = 1
463 ],
464 /// Transmitter/receiver
465 UCTR OFFSET(4) NUMBITS(1) [
466 /// Receiver
467 Receiver = 0,
468 /// Transmitter
469 Transmitter = 1
470 ],
471 /// Transmit ACK condition in slave mode
472 UCTXACK OFFSET(5) NUMBITS(1) [
473 /// Do not acknowledge the slave address
474 DoNotAcknowledgeTheSlaveAddress = 0,
475 /// Acknowledge the slave address
476 AcknowledgeTheSlaveAddress = 1
477 ],
478 /// eUSCI_B clock source select
479 UCSSEL OFFSET(6) NUMBITS(2) [
480 /// UCLKI
481 UCLKI = 0,
482 /// ACLK
483 ACLK = 1,
484 /// SMCLK
485 SMCLK = 2
486 ],
487 /// Synchronous mode enable
488 UCSYNC OFFSET(8) NUMBITS(1) [
489 /// Asynchronous mode
490 AsynchronousMode = 0,
491 /// Synchronous mode
492 SynchronousMode = 1
493 ],
494 /// eUSCI_B mode
495 UCMODE OFFSET(9) NUMBITS(2) [
496 /// 3-pin SPI
497 _3PinSPI = 0,
498 /// 4-pin SPI (master or slave enabled if STE = 1)
499 _4PinSPIMasterOrSlaveEnabledIfSTE1 = 1,
500 /// 4-pin SPI (master or slave enabled if STE = 0)
501 _4PinSPIMasterOrSlaveEnabledIfSTE0 = 2,
502 /// I2C mode
503 I2CMode = 3
504 ],
505 /// Master mode select
506 UCMST OFFSET(11) NUMBITS(1) [
507 /// Slave mode
508 SlaveMode = 0,
509 /// Master mode
510 MasterMode = 1
511 ],
512 /// Multi-master environment select
513 UCMM OFFSET(13) NUMBITS(1) [
514 /// Single master environment. There is no other master in the system. The address c
515 SingleMasterEnvironment = 0,
516 /// Multi-master environment
517 MultiMasterEnvironment = 1
518 ],
519 /// Slave addressing mode select
520 UCSLA10 OFFSET(14) NUMBITS(1) [
521 /// Address slave with 7-bit address
522 AddressSlaveWith7BitAddress = 0,
523 /// Address slave with 10-bit address
524 AddressSlaveWith10BitAddress = 1
525 ],
526 /// Own addressing mode select
527 UCA10 OFFSET(15) NUMBITS(1) [
528 /// Own address is a 7-bit address
529 OwnAddressIsA7BitAddress = 0,
530 /// Own address is a 10-bit address
531 OwnAddressIsA10BitAddress = 1
532 ]
533 ],
534 pub(crate) UCBxCTLW1 [
535 /// Deglitch time
536 UCGLIT OFFSET(0) NUMBITS(2) [
537 /// 50 ns
538 _50ns = 0,
539 /// 25 ns
540 _25ns = 1,
541 /// 12.5 ns
542 _125ns = 2,
543 /// 6.25 ns
544 _625ns = 3
545 ],
546 /// Automatic STOP condition generation
547 UCASTP OFFSET(2) NUMBITS(2) [
548 /// No automatic STOP generation. The STOP condition is generated after the user set
549 Manual = 0,
550 /// UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCN
551 ByteCounterInterrupt = 1,
552 /// A STOP condition is generated automatically after the byte counter value reached
553 ByteCounterStopCondition = 2
554 ],
555 /// SW or HW ACK control
556 UCSWACK OFFSET(4) NUMBITS(1) [
557 /// The address acknowledge of the slave is controlled by the eUSCI_B module
558 HardwareTriggered = 0,
559 /// The user needs to trigger the sending of the address ACK by issuing UCTXACK
560 SoftwareTriggered = 1
561 ],
562 /// ACK all master bytes
563 UCSTPNACK OFFSET(5) NUMBITS(1) [
564 /// Send a non-acknowledge before the STOP condition as a master receiver (conform t
565 NackBeforeStop = 0,
566 /// All bytes are acknowledged by the eUSCI_B when configured as master receiver
567 AckBeforeStop = 1
568 ],
569 /// Clock low timeout select
570 UCCLTO OFFSET(6) NUMBITS(2) [
571 /// Disable clock low timeout counter
572 DisableClockLowTimeoutCounter = 0,
573 /// 135 000 SYSCLK cycles (approximately 28 ms)
574 _135000SYSCLKCyclesApproximately28Ms = 1,
575 /// 150 000 SYSCLK cycles (approximately 31 ms)
576 _150000SYSCLKCyclesApproximately31Ms = 2,
577 /// 165 000 SYSCLK cycles (approximately 34 ms)
578 _165000SYSCLKCyclesApproximately34Ms = 3
579 ],
580 /// Early UCTXIFG0
581 UCETXINT OFFSET(8) NUMBITS(1) [
582 /// UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indi
583 UCETXINT_0 = 0,
584 /// UCTXIFG0 is set for each START condition
585 UCTXIFG0IsSetForEachSTARTCondition = 1
586 ]
587 ],
588 pub(crate) UCBxSTATW [
589 /// Bus busy
590 UCBBUSY OFFSET(4) NUMBITS(1) [
591 /// Bus inactive
592 BusInactive = 0,
593 /// Bus busy
594 BusBusy = 1
595 ],
596 /// General call address received
597 UCGC OFFSET(5) NUMBITS(1) [
598 /// No general call address received
599 NoGeneralCallAddressReceived = 0,
600 /// General call address received
601 GeneralCallAddressReceived = 1
602 ],
603 /// SCL low
604 UCSCLLOW OFFSET(6) NUMBITS(1) [
605 /// SCL is not held low
606 SCLIsNotHeldLow = 0,
607 /// SCL is held low
608 SCLIsHeldLow = 1
609 ],
610 /// Hardware byte counter value
611 UCBCNT OFFSET(8) NUMBITS(8) []
612 ],
613 pub(crate) UCBxI2COA0 [
614 /// I2C own address
615 I2COA0 OFFSET(0) NUMBITS(10) [],
616 /// Own Address enable register
617 UCOAEN OFFSET(10) NUMBITS(1) [
618 /// The slave address defined in I2COA0 is disabled
619 TheSlaveAddressDefinedInI2COA0IsDisabled = 0,
620 /// The slave address defined in I2COA0 is enabled
621 TheSlaveAddressDefinedInI2COA0IsEnabled = 1
622 ],
623 /// General call response enable
624 UCGCEN OFFSET(15) NUMBITS(1) [
625 /// Do not respond to a general call
626 DoNotRespondToAGeneralCall = 0,
627 /// Respond to a general call
628 RespondToAGeneralCall = 1
629 ]
630 ],
631 pub(crate) UCBxI2COA1 [
632 /// I2C own address
633 I2COA1 OFFSET(0) NUMBITS(10) [],
634 /// Own Address enable register
635 UCOAEN OFFSET(10) NUMBITS(1) [
636 /// The slave address defined in I2COA1 is disabled
637 TheSlaveAddressDefinedInI2COA1IsDisabled = 0,
638 /// The slave address defined in I2COA1 is enabled
639 TheSlaveAddressDefinedInI2COA1IsEnabled = 1
640 ]
641 ],
642 pub(crate) UCBxI2COA2 [
643 /// I2C own address
644 I2COA2 OFFSET(0) NUMBITS(10) [],
645 /// Own Address enable register
646 UCOAEN OFFSET(10) NUMBITS(1) [
647 /// The slave address defined in I2COA2 is disabled
648 TheSlaveAddressDefinedInI2COA2IsDisabled = 0,
649 /// The slave address defined in I2COA2 is enabled
650 TheSlaveAddressDefinedInI2COA2IsEnabled = 1
651 ]
652 ],
653 pub(crate) UCBxI2COA3 [
654 /// I2C own address
655 I2COA3 OFFSET(0) NUMBITS(10) [],
656 /// Own Address enable register
657 UCOAEN OFFSET(10) NUMBITS(1) [
658 /// The slave address defined in I2COA3 is disabled
659 TheSlaveAddressDefinedInI2COA3IsDisabled = 0,
660 /// The slave address defined in I2COA3 is enabled
661 TheSlaveAddressDefinedInI2COA3IsEnabled = 1
662 ]
663 ],
664 pub(crate) UCBxIE [
665 /// Receive interrupt enable 0
666 UCRXIE0 OFFSET(0) NUMBITS(1) [
667 /// Interrupt disabled
668 InterruptDisabled = 0,
669 /// Interrupt enabled
670 InterruptEnabled = 1
671 ],
672 /// Transmit interrupt enable 0
673 UCTXIE0 OFFSET(1) NUMBITS(1) [
674 /// Interrupt disabled
675 InterruptDisabled = 0,
676 /// Interrupt enabled
677 InterruptEnabled = 1
678 ],
679 /// START condition interrupt enable
680 UCSTTIE OFFSET(2) NUMBITS(1) [
681 /// Interrupt disabled
682 InterruptDisabled = 0,
683 /// Interrupt enabled
684 InterruptEnabled = 1
685 ],
686 /// STOP condition interrupt enable
687 UCSTPIE OFFSET(3) NUMBITS(1) [
688 /// Interrupt disabled
689 InterruptDisabled = 0,
690 /// Interrupt enabled
691 InterruptEnabled = 1
692 ],
693 /// Arbitration lost interrupt enable
694 UCALIE OFFSET(4) NUMBITS(1) [
695 /// Interrupt disabled
696 InterruptDisabled = 0,
697 /// Interrupt enabled
698 InterruptEnabled = 1
699 ],
700 /// Not-acknowledge interrupt enable
701 UCNACKIE OFFSET(5) NUMBITS(1) [
702 /// Interrupt disabled
703 InterruptDisabled = 0,
704 /// Interrupt enabled
705 InterruptEnabled = 1
706 ],
707 /// Byte counter interrupt enable
708 UCBCNTIE OFFSET(6) NUMBITS(1) [
709 /// Interrupt disabled
710 InterruptDisabled = 0,
711 /// Interrupt enabled
712 InterruptEnabled = 1
713 ],
714 /// Clock low timeout interrupt enable
715 UCCLTOIE OFFSET(7) NUMBITS(1) [
716 /// Interrupt disabled
717 InterruptDisabled = 0,
718 /// Interrupt enabled
719 InterruptEnabled = 1
720 ],
721 /// Receive interrupt enable 1
722 UCRXIE1 OFFSET(8) NUMBITS(1) [
723 /// Interrupt disabled
724 InterruptDisabled = 0,
725 /// Interrupt enabled
726 InterruptEnabled = 1
727 ],
728 /// Transmit interrupt enable 1
729 UCTXIE1 OFFSET(9) NUMBITS(1) [
730 /// Interrupt disabled
731 InterruptDisabled = 0,
732 /// Interrupt enabled
733 InterruptEnabled = 1
734 ],
735 /// Receive interrupt enable 2
736 UCRXIE2 OFFSET(10) NUMBITS(1) [
737 /// Interrupt disabled
738 InterruptDisabled = 0,
739 /// Interrupt enabled
740 InterruptEnabled = 1
741 ],
742 /// Transmit interrupt enable 2
743 UCTXIE2 OFFSET(11) NUMBITS(1) [
744 /// Interrupt disabled
745 InterruptDisabled = 0,
746 /// Interrupt enabled
747 InterruptEnabled = 1
748 ],
749 /// Receive interrupt enable 3
750 UCRXIE3 OFFSET(12) NUMBITS(1) [
751 /// Interrupt disabled
752 InterruptDisabled = 0,
753 /// Interrupt enabled
754 InterruptEnabled = 1
755 ],
756 /// Transmit interrupt enable 3
757 UCTXIE3 OFFSET(13) NUMBITS(1) [
758 /// Interrupt disabled
759 InterruptDisabled = 0,
760 /// Interrupt enabled
761 InterruptEnabled = 1
762 ],
763 /// Bit position 9 interrupt enable
764 UCBIT9IE OFFSET(14) NUMBITS(1) [
765 /// Interrupt disabled
766 InterruptDisabled = 0,
767 /// Interrupt enabled
768 InterruptEnabled = 1
769 ]
770 ],
771 pub(crate) UCBxIFG [
772 /// eUSCI_B receive interrupt flag 0
773 UCRXIFG0 OFFSET(0) NUMBITS(1) [
774 /// No interrupt pending
775 NoInterruptPending = 0,
776 /// Interrupt pending
777 InterruptPending = 1
778 ],
779 /// eUSCI_B transmit interrupt flag 0
780 UCTXIFG0 OFFSET(1) NUMBITS(1) [
781 /// No interrupt pending
782 NoInterruptPending = 0,
783 /// Interrupt pending
784 InterruptPending = 1
785 ],
786 /// START condition interrupt flag
787 UCSTTIFG OFFSET(2) NUMBITS(1) [
788 /// No interrupt pending
789 NoInterruptPending = 0,
790 /// Interrupt pending
791 InterruptPending = 1
792 ],
793 /// STOP condition interrupt flag
794 UCSTPIFG OFFSET(3) NUMBITS(1) [
795 /// No interrupt pending
796 NoInterruptPending = 0,
797 /// Interrupt pending
798 InterruptPending = 1
799 ],
800 /// Arbitration lost interrupt flag
801 UCALIFG OFFSET(4) NUMBITS(1) [
802 /// No interrupt pending
803 NoInterruptPending = 0,
804 /// Interrupt pending
805 InterruptPending = 1
806 ],
807 /// Not-acknowledge received interrupt flag
808 UCNACKIFG OFFSET(5) NUMBITS(1) [
809 /// No interrupt pending
810 NoInterruptPending = 0,
811 /// Interrupt pending
812 InterruptPending = 1
813 ],
814 /// Byte counter interrupt flag
815 UCBCNTIFG OFFSET(6) NUMBITS(1) [
816 /// No interrupt pending
817 NoInterruptPending = 0,
818 /// Interrupt pending
819 InterruptPending = 1
820 ],
821 /// Clock low timeout interrupt flag
822 UCCLTOIFG OFFSET(7) NUMBITS(1) [
823 /// No interrupt pending
824 NoInterruptPending = 0,
825 /// Interrupt pending
826 InterruptPending = 1
827 ],
828 /// eUSCI_B receive interrupt flag 1
829 UCRXIFG1 OFFSET(8) NUMBITS(1) [
830 /// No interrupt pending
831 NoInterruptPending = 0,
832 /// Interrupt pending
833 InterruptPending = 1
834 ],
835 /// eUSCI_B transmit interrupt flag 1
836 UCTXIFG1 OFFSET(9) NUMBITS(1) [
837 /// No interrupt pending
838 NoInterruptPending = 0,
839 /// Interrupt pending
840 InterruptPending = 1
841 ],
842 /// eUSCI_B receive interrupt flag 2
843 UCRXIFG2 OFFSET(10) NUMBITS(1) [
844 /// No interrupt pending
845 NoInterruptPending = 0,
846 /// Interrupt pending
847 InterruptPending = 1
848 ],
849 /// eUSCI_B transmit interrupt flag 2
850 UCTXIFG2 OFFSET(11) NUMBITS(1) [
851 /// No interrupt pending
852 NoInterruptPending = 0,
853 /// Interrupt pending
854 InterruptPending = 1
855 ],
856 /// eUSCI_B receive interrupt flag 3
857 UCRXIFG3 OFFSET(12) NUMBITS(1) [
858 /// No interrupt pending
859 NoInterruptPending = 0,
860 /// Interrupt pending
861 InterruptPending = 1
862 ],
863 /// eUSCI_B transmit interrupt flag 3
864 UCTXIFG3 OFFSET(13) NUMBITS(1) [
865 /// No interrupt pending
866 NoInterruptPending = 0,
867 /// Interrupt pending
868 InterruptPending = 1
869 ],
870 /// Bit position 9 interrupt flag
871 UCBIT9IFG OFFSET(14) NUMBITS(1) [
872 /// No interrupt pending
873 NoInterruptPending = 0,
874 /// Interrupt pending
875 InterruptPending = 1
876 ]
877 ],
878 pub(crate) UCBxIV [
879 UCIV OFFSET(0) NUMBITS(16) [
880 NoInterrupt = 0x00,
881 ArbitrationLost = 0x02,
882 NoAck = 0x04,
883 ReceivedStartCondition = 0x06,
884 ReceivedStopCondition = 0x08,
885 Slave3DataReceived = 0x0A,
886 Slave3TransmitBufferEmpty = 0x0C,
887 Slave2DataReceived = 0x0E,
888 Slave2TransmitBufferEmpty = 0x10,
889 Slave1DataReceived = 0x12,
890 Slave1TransmitBufferEmpty = 0x14,
891 DataReceived = 0x16,
892 TransmitBufferEmpty = 0x18,
893 ByteCounterZero = 0x1A,
894 ClockLowTimeout = 0x1C,
895 NinethBitPosition = 0x1E
896 ]
897 ]
898];