msp432/
nvic.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Nested Vector Interrupt Controller (NVIC)
6
7pub const PSS: u32 = 0;
8pub const CS: u32 = 1;
9pub const PCM: u32 = 2;
10pub const WDT_A: u32 = 3;
11pub const FPU_INT: u32 = 4;
12pub const FLCTL: u32 = 5;
13pub const CMP_E0: u32 = 6;
14pub const CMP_E1: u32 = 7;
15pub const TIMER_A0_0: u32 = 8;
16pub const TIMER_A0_1: u32 = 9;
17pub const TIMER_A1_0: u32 = 10;
18pub const TIMER_A1_1: u32 = 11;
19pub const TIMER_A2_0: u32 = 12;
20pub const TIMER_A2_1: u32 = 13;
21pub const TIMER_A3_0: u32 = 14;
22pub const TIMER_A3_1: u32 = 15;
23pub const USCI_A0: u32 = 16;
24pub const USCI_A1: u32 = 17;
25pub const USCI_A2: u32 = 18;
26pub const USCI_A3: u32 = 19;
27pub const USCI_B0: u32 = 20;
28pub const USCI_B1: u32 = 21;
29pub const USCI_B2: u32 = 22;
30pub const USCI_B3: u32 = 23;
31pub const ADC: u32 = 24;
32pub const TIMER32_INT1: u32 = 25;
33pub const TIMER32_INT2: u32 = 26;
34pub const TIMER32_COMBINED: u32 = 27;
35pub const AES256: u32 = 28;
36pub const RTC: u32 = 29;
37pub const DMA_ERR: u32 = 30;
38pub const DMA_INT3: u32 = 31;
39pub const DMA_INT2: u32 = 32;
40pub const DMA_INT1: u32 = 33;
41pub const DMA_INT0: u32 = 34;
42pub const IO_PORT1: u32 = 35;
43pub const IO_PORT2: u32 = 36;
44pub const IO_PORT3: u32 = 37;
45pub const IO_PORT4: u32 = 38;
46pub const IO_PORT5: u32 = 39;
47pub const IO_PORT6: u32 = 40;