arty_e21_chip/
gpio.rs

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1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use core::ops::{Index, IndexMut};
6
7use kernel::utilities::StaticRef;
8pub use sifive::gpio::GpioPin;
9use sifive::gpio::{pins, GpioRegisters};
10
11pub const GPIO0_BASE: StaticRef<GpioRegisters> =
12    unsafe { StaticRef::new(0x2000_2000 as *const GpioRegisters) };
13
14pub struct Port<'a> {
15    pins: [GpioPin<'a>; 16],
16}
17
18impl<'a> Index<usize> for Port<'a> {
19    type Output = GpioPin<'a>;
20
21    fn index(&self, index: usize) -> &GpioPin<'a> {
22        &self.pins[index]
23    }
24}
25
26impl<'a> IndexMut<usize> for Port<'a> {
27    fn index_mut(&mut self, index: usize) -> &mut GpioPin<'a> {
28        &mut self.pins[index]
29    }
30}
31
32impl Port<'_> {
33    pub fn new() -> Self {
34        Self {
35            pins: [
36                GpioPin::new(GPIO0_BASE, pins::pin0, pins::pin0::SET, pins::pin0::CLEAR),
37                GpioPin::new(GPIO0_BASE, pins::pin1, pins::pin1::SET, pins::pin1::CLEAR),
38                GpioPin::new(GPIO0_BASE, pins::pin2, pins::pin2::SET, pins::pin2::CLEAR),
39                GpioPin::new(GPIO0_BASE, pins::pin3, pins::pin3::SET, pins::pin3::CLEAR),
40                GpioPin::new(GPIO0_BASE, pins::pin4, pins::pin4::SET, pins::pin4::CLEAR),
41                GpioPin::new(GPIO0_BASE, pins::pin5, pins::pin5::SET, pins::pin5::CLEAR),
42                GpioPin::new(GPIO0_BASE, pins::pin6, pins::pin6::SET, pins::pin6::CLEAR),
43                GpioPin::new(GPIO0_BASE, pins::pin7, pins::pin7::SET, pins::pin7::CLEAR),
44                GpioPin::new(GPIO0_BASE, pins::pin8, pins::pin8::SET, pins::pin8::CLEAR),
45                GpioPin::new(GPIO0_BASE, pins::pin9, pins::pin9::SET, pins::pin9::CLEAR),
46                GpioPin::new(
47                    GPIO0_BASE,
48                    pins::pin10,
49                    pins::pin10::SET,
50                    pins::pin10::CLEAR,
51                ),
52                GpioPin::new(
53                    GPIO0_BASE,
54                    pins::pin11,
55                    pins::pin11::SET,
56                    pins::pin11::CLEAR,
57                ),
58                GpioPin::new(
59                    GPIO0_BASE,
60                    pins::pin12,
61                    pins::pin12::SET,
62                    pins::pin12::CLEAR,
63                ),
64                GpioPin::new(
65                    GPIO0_BASE,
66                    pins::pin13,
67                    pins::pin13::SET,
68                    pins::pin13::CLEAR,
69                ),
70                GpioPin::new(
71                    GPIO0_BASE,
72                    pins::pin14,
73                    pins::pin14::SET,
74                    pins::pin14::CLEAR,
75                ),
76                GpioPin::new(
77                    GPIO0_BASE,
78                    pins::pin15,
79                    pins::pin15::SET,
80                    pins::pin15::CLEAR,
81                ),
82            ],
83        }
84    }
85}
arty_e21_chip/gpio.rs

arty_e21_chip/
gpio.rs
