Interfaces for SPI controller (master) and peripheral (slave) communication. We use the terms master/slave in some situations because the term peripheral can also refer to a hardware peripheral (e.g., memory-mapped I/O devices in ARM are called peripherals).
Clock phase (CPHA) defines whether to sample and send data on a leading or trailing clock edge; consult a SPI reference on how CPHA interacts with CPOL.
Clock polarity (CPOL) defines whether the SPI clock is high or low when idle.
Data order defines the order of bits sent over the wire: most significant first, or least significant first.
SpiMaster trait for interacting with SPI slave
devices at a byte or buffer level.
Trait for clients of a SPI bus in master mode.
SPIMasterDevice provides a chip-select-specific interface to the SPI Master hardware, such that a client cannot changethe chip select line.
Trait for SPI peripherals (slaves) to exchange data with a contoller
(master). This is a low-level trait typically implemented by hardware:
higher level software typically uses the
which is provided by a virtualizing/multiplexing layer.
Trait for SPI peripherals (slaves) to receive callbacks when the
corresponding controller (master) issues operations. A SPI operation
begins with a callback of
chip_selected. If the client has
provided buffers with
SpiSlave::read_write_bytes, these buffers
are written from and read into until the operation completes or one
of them fills, at which point a
callback is called. If the client needs to read/write more it
SpiSlave::read_write_bytes again. Note that there is
no notification when the chip select line goes high.
SPISlaveDevice is an interface to a SPI bus in peripheral mode.
It is the standard trait used by services within the kernel:
SpiSlave is for lower-level access responsible for initializing