Trait kernel::hil::spi::SpiMasterDevice

pub trait SpiMasterDevice<'a> {
    // Required methods
    fn set_client(&self, client: &'a dyn SpiMasterClient);
    fn configure(
        &self,
        cpol: ClockPolarity,
        cpal: ClockPhase,
        rate: u32,
    ) -> Result<(), ErrorCode>;
    fn read_write_bytes(
        &self,
        write_buffer: SubSliceMut<'static, u8>,
        read_buffer: Option<SubSliceMut<'static, u8>>,
    ) -> Result<(), (ErrorCode, SubSliceMut<'static, u8>, Option<SubSliceMut<'static, u8>>)>;
    fn set_rate(&self, rate: u32) -> Result<(), ErrorCode>;
    fn get_rate(&self) -> u32;
    fn set_polarity(&self, polarity: ClockPolarity) -> Result<(), ErrorCode>;
    fn get_polarity(&self) -> ClockPolarity;
    fn set_phase(&self, phase: ClockPhase) -> Result<(), ErrorCode>;
    fn get_phase(&self) -> ClockPhase;
}

A chip-select-specific interface to the SPI Controller hardware, such that a client cannot change the chip select line.

This restricts the SPI peripherals the client can access to a specific peripheral.

Required Methods

fn set_client(&self, client: &'a dyn SpiMasterClient)

Set the callback for read_write operations.

fn configure( &self, cpol: ClockPolarity, cpal: ClockPhase, rate: u32, ) -> Result<(), ErrorCode>

Configure the bus for this chip select.

fn read_write_bytes( &self, write_buffer: SubSliceMut<'static, u8>, read_buffer: Option<SubSliceMut<'static, u8>>, ) -> Result<(), (ErrorCode, SubSliceMut<'static, u8>, Option<SubSliceMut<'static, u8>>)>

Same as SpiMaster::read_write_bytes.

fn set_rate(&self, rate: u32) -> Result<(), ErrorCode>

Same as SpiMaster::set_rate.

fn get_rate(&self) -> u32

Return the current chip select’s clock rate.

fn set_polarity(&self, polarity: ClockPolarity) -> Result<(), ErrorCode>

Same as SpiMaster::set_polarity.

fn get_polarity(&self) -> ClockPolarity

Return the current bus polarity.

fn set_phase(&self, phase: ClockPhase) -> Result<(), ErrorCode>

Same as SpiMaster::set_phase.

fn get_phase(&self) -> ClockPhase

Get the current bus phase for the current chip select.

Implementors