Struct Pc

pub struct Pc<'a, I: InterruptService + 'a, const PR: u16 = RELOAD_1KHZ> {
    pub com1: &'a SerialPort<'a>,
    pub com2: &'a SerialPort<'a>,
    pub com3: &'a SerialPort<'a>,
    pub com4: &'a SerialPort<'a>,
    pub pit: Pit<'a, PR>,
    pub vga: &'a VgaText<'a>,
    /* private fields */
}

Representation of a generic PC platform.

This struct serves as an implementation of Tock’s Chip trait for the x86 PC platform. The behavior and set of peripherals available on PCs is very heavily standardized. As a result, this chip definition should be broadly compatible with most PC hardware.

Parameter PR is the PIT reload value. See Pit for more information.

Interrupt Handling

This chip automatically handles interrupts for legacy PC devices which are known to be present on QEMU’s Q35 machine type. This includes the PIT timer and four serial ports. Other devices which are conditionally present (e.g. Virtio devices specified on the QEMU command line) may be handled via a board-specific implementation of InterruptService.

This chip uses the legacy 8259 PIC to manage interrupts. This is relatively simple compared with using the Local APIC or I/O APIC and avoids needing to interact with ACPI or MP tables.

Internally, this chip re-maps the PIC interrupt numbers to avoid conflicts with ISA-defined exceptions. This remapping is fully encapsulated within the chip. N.B. Implementors of InterruptService will be passed the physical interrupt line number, not the remapped number used internally by the chip. This should match the interrupt line number reported by documentation or read from the PCI configuration space.

Fields

com1: &'a SerialPort<'a>

Legacy COM1 serial port

com2: &'a SerialPort<'a>

Legacy COM2 serial port

com3: &'a SerialPort<'a>

Legacy COM3 serial port

com4: &'a SerialPort<'a>

Legacy COM4 serial port

pit: Pit<'a, PR>

Legacy PIT timer

vga: &'a VgaText<'a>

Vga

Trait Implementations

impl<'a, I: InterruptService + 'a, const PR: u16> Chip for Pc<'a, I, PR>

type ThreadIdProvider = X86ThreadIdProvider

Provider to query the currently running thread ID.

type MPU = PagingMPU<'a>

The particular Memory Protection Unit (MPU) for this chip.

type UserspaceKernelBoundary = Boundary

The implementation of the interface between userspace and the kernel for this specific chip. Likely this is architecture specific, but individual chips may have various custom requirements.

fn mpu(&self) -> &Self::MPU

Returns a reference to the implementation for the MPU on this chip.

fn userspace_kernel_boundary(&self) -> &Self::UserspaceKernelBoundary

Returns a reference to the implementation for the interface between userspace and kernelspace.

fn service_pending_interrupts(&self)

The kernel calls this function to tell the chip to check for all pending interrupts and to correctly dispatch them to the peripheral drivers for the chip.

fn has_pending_interrupts(&self) -> bool

Ask the chip to check if there are any pending interrupts.

fn sleep(&self)

Called when there is nothing left for the chip to do and it should enter a low power sleep state. This low power sleep state should allow interrupts to still be active so that the next interrupt event wakes the chip and resumes the scheduler.

unsafe fn with_interrupts_disabled<F, R>(&self, f: F) -> R

where F: FnOnce() -> R,

Run a function in an atomic state w.r.t. to the current core. This means that interrupts are disabled so that an interrupt will not fire during the passed in function’s execution, but does not make any guarantees about memory consistency on a multi-core system.

unsafe fn print_state(&self, writer: &mut dyn Write)

Print out chip state (system registers) to a supplied writer. This does not print out the execution context (data registers), as this depends on how they are stored; that is implemented by syscall::UserspaceKernelBoundary::print_context. This also does not print out a process memory state, that is implemented by process::Process::print_memory_map. The MPU state is printed by the MPU’s implementation of the Display trait. Used by panic.